Fifteen years ago, designers were buzzing about a new design approach: Register Transfer Level (RTL) Design. There was a fundamental change underway in how chip designs were created and implemented. There were methodology experts within electronics companies whose sole responsibility was to move design teams to using RTL design methods. It was this focus that enabled the methodology shift the industry experienced and changed the way chips were designed.
Back then, the average chip had tens of thousands of gates and took 18 to 24 months to design. Fast forward to 2007 and, while the average gate count is now in the tens of millions, design cycle requirements have been slashed to six to nine months. Still, the majority of U.S. design teams are using a design methodology similar to what was used in the 1990s.
While RTL design was and still is an important engineering methodology development, new technologies and standards are forcing continued evolution. But, what happened to our methodology experts?
In more progressive companies, particularly in Europe and in Asia, well-staffed methodology teams have been assembled to drive electronic system-level (ESL) methods into their respective companies. Working with EDA partners, these teams are able to understand how best to roll out ESL methodologies that provide the most immediate benefit. The phasing of adoption allows for software and hardware teams to initially take advantage of the "low-hanging" ESL fruit. Over time, they can take on some of the more dramatic methodology changes that provide substantial return on investment. These companies have also been able to influence ESL suppliers on the prioritization of "wish list" features and capabilities they feel will provide the greatest benefit.
The key to success for these companies is resolve of visionary leaders to assign their highest caliber engineers to the task of driving ESL adoption.
The results of these efforts are impressive and have spurred the leading consumer electronics companies to move to ESL design. Productivity gains are substantial with documented time-to-market improvements in the range of four to six months. Design errors previously found late in the design flow are now found during initial system-level design exploration. Accurate system-level models used for both software development and system-on-chip implementation have resolved the performance disconnect between hardware and software design environments.
In Japan, nearly every major consumer electronics company has adopted ESL as part of their mainstream design flow. Changes in requirements that took weeks to implement in a traditional RTL design flow can now be accomplished in hours. The verification of functions, which required days or weeks of simulation across multiple servers, can now be accomplished in hours using formal system-level design verification techniques.
What is limiting full-scale ESL adoption in the U.S.?
At this point, the key benefactors of ESL, namely electronics companies developing wireless and consumer products, have not come to grips with what it takes to make a wholesale investment in changing the way product design is accomplished. These companies must realize that just as moving from gate-level design to RTL design required a methodology and skill change, so does the move to an ESL design methodology.