Design Con 2015
Breaking News
Design How-To

Universal memory, round two

11/8/2009 05:00 AM EST
1 Comment
NO RATINGS
Page 1 / 4 Next >
More Related Links
View Comments: Newest First | Oldest First | Threaded View
Semiconductor Analyst
User Rank
Rookie
re: Universal memory, round two
Semiconductor Analyst   11/10/2009 1:32:38 PM
NO RATINGS
I would not bet against NAND for the foreseeable future. So while lithographic scaling will be a problem sub 32 nm, that problem is faced by everyone. And yes it will be hard to scale the interpoly dielectric and tunnel oxides. But HfO or AlO are being used in DRAMs and microprocessors. And Samsung and Toshiba have been qute clever at migrating to 2, 3, and 4 bits per cell. That and multichip packaging (I think one vendor has shown 9 dies in a stack) would suggest that flash has a way to go before bust. I don't see any of the other memory technologies as having the kind of infrastructure that flash and DRAM have. The reports of flash/DRAM deaths are quite premature.

Radio
LATEST ARCHIVED BROADCAST
EE Times Senior Technical Editor Martin Rowe will interview EMC engineer Kenneth Wyatt.
Top Comments of the Week
Like Us on Facebook

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Times on Twitter
EE Times Twitter Feed
Flash Poll