As the process technology nodes keep shrinking, the variation of the design parameters transition, such as cell delays, becomes non-linear across different process, voltage and temperature (PVT) corners. As a result, we face the following problems during timing closure:
(1) A path can be setup critical in one corner, and hold critical in some other corner;
(2) A different set of timing paths can become critical in different corners.
We have tried to address these concerns with our unique concept of comparing the ratios of clock and data path cells across the PVTs.
The traditional timing closure flow includes fixing setup violations across the worst case corner and fixing hold violations across the best case corner. With the advent of shrinking technology, the number of PVT corners increases, making it difficult to identify the worst paths (for both setup and hold).
There can be timing paths that are both setup and hold critical, which then make it difficult to fix the violations. This can lead to multiple iterations, inefficient optimization that lowers the Quality of Results (QoR) of the design and increases the new product introduction (NPI) cycle time.
To address these issues, we shall try to determine library cells that have more or less the same variation in different problem scenarios.
Problem Scenario # 1: Timing across worst & best PVT setup/hold violations
Traditional methods involve fixing timing across the worst PVT for setup violations and across the best PVT for hold violations. With this approach, we can have paths that are critical for both setup and hold constraints. Figure 1 below depicts this problem.
The reason for this problem can be discovered if we analyze the figure closely. The variation in data path and clock paths are not the same across both the corners. The ratio of data variation is
4.726/1.584 = 2.98.
The variation of the clock path delay is,
3.793/1.674 = 2.26
Problem Scenario #2: Different sets of timing paths becoming critical in corners
Another problem that can arise is different sets of timing paths becoming critical in different corners, thereby increasing the number of timing paths on which timing closure will have to be done. This is depicted in Figure 2 below.
It would be impossible to decide which PVT corner is the worst to optimize. This problem arises due to the difference in the delay variation across different PVTs. Delay variation of an AND cell might be different when compared to an XOR cell, and so on and so forth.