Cadence and Mentor Graphics recently announced and shipped the Open Verification Methodology (OVM). This initiative focuses on providing a single, open, and interoperable SystemVerilog-based methodology and supporting class library. But why introduce a new methodology now? With at least three other SystemVerilog methodologies already available, why add another to the mix?
The simple answer is that goal of the OVM is to reduce the number of methodologies available, thereby improving the productivity of SystemVerilog users, including designers, verification engineers, VIP providers, and even EDA vendors. In order to achieve this, OVM must be completely open, enable full interoperability, provide advanced functionality, and offer a long-term growth path.
The SystemVerilog Language Race is Over
When SystemVerilog was standardized over four years ago, users liked the idea of a single language with constructs to handle not just design, but verification as well. As simulation vendors started implementing these features, customers started using them and asking for others. This trend continued for several years, as customers pushed vendors to support the language constructs they needed. But what happened along the way was a shift from needing language constructs to a requirement to build a reusable verification environment. Customers realized that the important factor was how they built the environment, not which language constructs were involved.
Fast forward to today when we see that most of the testbench language constructs have been implemented in simulation tools. In order to deliver on the original promise of SystemVerilog, what is needed is the ability to create modular verification environments that can use verification IP (VIP) components that have been created somewhere else - either on another project within the company or by an external source such as a partner or a VIP supplier.
What Does Interoperability Really Mean?
In the past, users often believed that interoperability meant language compatibility across simulators. If the simulator could run the same code and produce the same result, that was sufficient. And this is still largely true for the RTL design. But now that SystemVerilog encompasses the verification environment as well, the definition of interoperability becomes more complex.
Firstly, the need for reuse has risen dramatically. As designs grow larger and design teams grow smaller, reuse has become a near necessity. Reuse of RTL is fairly straightforward, but at the verification level it is more difficult. Individual designers are building small verification suites to test their blocks, each different from all the others. Verification teams have the opportunity to build reusable verification environments, but don't always understand the best way to do it.
Secondly, reusable IP and VIP is becoming more available. Design IP is rigorously defined, in that it has a fixed pin-out and a clearly defined way of communicating via signals. For verification IP, there are a variety of ways that it can be constructed, and a near infinite-number of ways it can talk with the design, other VIP, and the overall verification environment.
What is really needed is true interoperability of the entire verification environment, not just with the SystemVerilog language.
Interoperability at the Methodology Level
To achieve this interoperability, verification engineers need a methodology that defines how components should be built. If all components are built in a similar fashion, then they can get the interoperability they are looking for. Users need to be able to build verification environments that can use VIP blocks that are built by different projects or even different companies. The new definition requires that the methodology is:
- Vendor-neutral in terms of SystemVerilog. Yes, a single LRM definition for SystemVerilog is still required; but it needs to be evaluated the same across all tools, not just supported. And it needs to be completely standard, not mostly standard with a few proprietary extensions added.
- Interoperable with other languages. It would be nave to ignore all the valuable IP already developed in the world in other languages such as SystemC, e, VHDL, and PSL.
- Completely open. Users need the ability to modify the methodology and library if necessary, and the security to know that using it won't lock them into a single set of tools.
- Flexibly licensed. Customers need to be able to freely exchange VIP without needing permission from their EDA vendor.
- Production Proven. The methodology must be capable of supporting real-world requirements and dealing with the complete design chain.
- Extendable. Even the best methodology needs to be flexible enough to allow for new challenges and future technologies.
Before the OVM, no existing methodology supported all these requirements. Existing implementations lacked simulator interoperability, had overly restrictive license agreements, or used proprietary language extensions. They also required verification components to be constructed differently, so no compatibility between them could occur. In order to truly deliver on the promise of SystemVerilog interoperability, something new and different was needed.
The OVM does address each of these requirements. It has been architected from the beginning to be open, use pure IEEE 1800 SystemVerilog, and have an open source license to provide users with maximum flexibility. It has been designed to work with the other major languages used for design and verification, and is verified on simulation platforms from Mentor Graphics and Cadence. Finally, the OVM is built on the proven techniques used in the Cadence Universal Reuse Methodology (URM) and Mentor Advanced Verification Methodology (AVM), with backwards compatibility to both of these methodologies. Mentor and Cadence are committed to continuing development to address future design and verification challenges.
It might seem as if the industry already had enough methodologies available to deal with today's design and verification needs. But in reality, the openness and interoperability required for reusable verification environments and VIP called for something different: an open, standards-based, flexible, and proven methodology to be able to achieve the true promise of interoperability that SystemVerilog promised the design and verification community. OVM delivers on that promise.
Pete Johnson, is currently a Director of Marketing at Cadence Design Systems, and was
involved in the formation of the OVM coalition. He can be reached at: firstname.lastname@example.org
Cadence and Mentor Enhance Open Verification Methodology
Cadence, Mentor team on SystemVerilog verification