You work in an environment where demanding design goals and aggressive project schedules go hand-in-hand with the push to get more complex products to market faster. And you have just finalized the RTL description of your company's next-generation product, a large system-on-chip (SoC). With just a few weeks remaining for final synthesis, place and route (P&R) and post-layout verification tasks, you wonder: can I still finish the job on schedule?
The answer depends on whether your synthesis solution is capable of delivering the best-possible quality-of-results (QoR) to meet all your timing, area, power and test requirements. Excellent QoR from synthesis is paramount to meeting your design objectives and cannot be compromised along the way. But given today's design challenges, this is a tall order. A robust synthesis solution must perform concurrent timing, area, power and test optimizations across multiple design corners and operating modes. To streamline the process, the synthesis engines can take advantage of the increased CPU parallelism now possible using inexpensive and widely-available multicore compute servers. Even so, your synthesis solution also must be able to accommodate a rich variety of design-for-test methodologies, low-power design techniques and a host of other design schemes that have emerged to meet the complex requirements of today's SoCs.
Synthesizing a netlist with the best QoR, however, is no longer enough to ensure fast design closure and a predictable schedule. As process geometries shrink to 65 nanometers, wire lengths and cell placement have a greater effect on critical timing paths in a design, leading to divergence of QoR between synthesis and place and route. The resulting uncorrelated design will invariably require changes to the layout (and often the RTL code itself) to meet your design requirements across all corners and modes of operation. And even if synthesis results are correlated, severe routing congestion can make it difficult to route the design. Design closure in this case will likely require extensive design alterations and successive iterations to converge to a routable design that also meets your performance specifications.
It is this convergence processthe numerous, time-consuming design iterations encompassing the entire implementation flowthat makes up most of the total implementation time and poses the greatest risk to your project schedule.
A robust synthesis solution, therefore, must be capable of producing results for timing, area and power that are correlated with place-and-route results, and that minimizes the occurrence of routing congestion.
Topographical technology within RTL synthesis can take advantage of virtual placement information to estimate wire lengths with sufficient accuracy to achieve the tight correlation needed for eliminating iterations and enabling rapid design closure. Moreover, congestion prediction and mitigation capabilities in the synthesis solution make it easy to identify potential congestion "hot spots," whether caused by the floorplan, or the presence of highly-interconnected logic structures in the netlist. Then, appropriate action can be taken up front by either altering the RTL, the floorplan or instructing synthesis to perform targeted congestion optimizations.