However, a new set of convergence challenges emerges below 65 nanometers. Coupling capacitances increase to such an extent that there is even less assurance that the timing results you achieve in synthesis will carry through to physical implementation. Therefore, maintaining close correlation between synthesis and layout becomes even more criticaland challenging.
To achieve the tighter correlation needed below 65 nanometers, the synthesis solution must not only take physical data and constraints into consideration, but also provide physical guidance to the place-and-route solution, generating a timing- and congestion-aware netlist with additional physical information the place-and-route tool can use to seed the placement. Also, because it is much more difficult to meet increasingly challenging design goals at these small geometries, floorplan exploration is routinely needed to converge on an optimal floorplan, leading to further project delays.
Guidance from synthesis to layout is most effective when the synthesis and place-and-route engines share the same algorithms and floorplanning capabilities. For example, access to floorplanning from within synthesis lets RTL designers perform what-if floorplan exploration to quickly identify and correct timing and congestion issues and converge on an optimal floorplan that would otherwise take much longer to complete in place and route. Passing guidance to place and route creates a better starting point for layout and preserves synthesis QoR downstream, accelerating the entire implementation flow by enabling both faster place-and-route runtimes and fewer design iterations.
If your synthesis solution can accomplish all this then, yes, you will likely tape out on schedule. As we have seen, synthesis must accommodate a spectrum of continually changing design methodologies while delivering on the promise of ever-better QoR and ever-tighter correlation with layout. Due to these complementary challenges, synthesis technology will continue to improve steadily but incrementally in the years ahead, in pace with design requirements that are constantly evolving.
About the author:
Eyal Odiz is vice president of engineering, RTL synthesis and test automation, Synopsys, Inc.
Odiz holds a bachelor of science in civil engineering, a bachelor of science in computer science, and a master of science in computer science, all from Technion in Haifa, Israel.