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An overview of SystemVerilog 3.1

An overview of SystemVerilog 3.1
5/21/2003 08:00 PM EDT
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Chiranjeevis
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Mistake is assertion:
Chiranjeevis   11/4/2013 6:46:45 AM
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always @ (posedge clock)
if(state == FETCH)
assert request_check;

you can't assert a sequence directly. It should be assert property, inside property we need to call the sequence temporial expression.

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