It was almost two years ago when four of us started FreeHand Communication, a semiconductor intellectual property (IP) company. We left Ericsson Microelectronics and formed FreeHand because we were convinced tasks existed in digital signal processing (DSP) where an application-specific DSP core would be the best option.
Traditionally, there are two ways to implement digital signal-processing functions. One is to use a general-purpose DSP core. The other is to use a nonprogrammable application-specific integrated circuit (ASIC) core. A general-purpose DSP core is not optimized for any particular task, but is flexible, while the ASIC core is customized for a specific task but offers no flexibility.
We chose to do something in between. Our DSP cores use a common platform, which contains a small reduced instruction set computing (RISC)-type processor designed by FreeHand and one or several accelerators, each dedicated to an application-specific task. These accelerators are small ASIC blocks that can be easily plugged into the platform. In this way, we can provide DSP application-specific solutions meant to be more efficient in terms of area, power consumption and performance compared with solutions based on general-purpose DSP cores. The flexibility remains intact because of the programmability.
In selecting a design methodology for our project, we realized that existing techniques and tools would fall short of the co-verification and C/hardware description language (HDL) co-simulation techniques we would require. An Instruction Set Simulator (ISS) representation of the device proved to be a key component for an effective hardware/software design approach. Fortunately, we came across electronic design automation (EDA) startup Co-Design Automation Inc. (Los Altos, Calif.), which was tackling these issues.
Co-Design Automation had developed a next-generation design language called Superlog, which evolved the Verilog HDL to handle verification and abstract design. Its simulator-Systemsim-could take as input C/C++, the Verilog HDL and Superlog, providing a single environment for fast, powerful verification and the seamless mixing of C/C++ models with HDL circuit descriptions. Most intriguing was the fact that members of the Co-Design team had helped design the Verilog language and simulator. Since C model usage and complex verification would be a key part of our design methodology, we scheduled a meeting to learn more.
As we were considering our design methodology, we initially thought we would use VHDL as our design language, because it is so popular in Europe. However, the larger IP market in the United States mostly used the Verilog HDL. Once we met with Co-Design and learned more about Superlog and Systemsim, we agreed that its tools would enable us to build a flexible, yet powerful, co-design environment, with many of the programming advantages of VHDL applied at a Verilog level of simplicity.
We optimized our first IP block for adaptive filtering at low-power consumption with echo cancellation as the main application. It was implemented as an 0.18-u process ASIC. Many existing DSP cores can handle echo cancellation, but they tend to be power hungry, larger and more expensive. We can put a number of DSP cores on a chip and handle many echo cancellation channels in parallel.
Before specifying the DSP core and its firmware, we built models of the various echo cancellation applications based on high-level languages (C and Matlab). We then transformed and refined the models into DSP-like structures and instructions, optimized for execution speed, gate count and power consumption.
Based on this, we wrote a traditional paper specification. From there, the DSP core was developed at the register transfer level (RTL) using the Verilog HDL. In parallel, we wrote an instruction set simulator (ISS) in C, providing our standard model. We produced the echo-canceling algorithm in assembler and verified using the ISS. We wrote the testbench for the system in Superlog, using Verilog-like verification capabilities.
During the simulation, we ran programs on both the ISS and the Verilog HDL-based design, and compared results after each instruction execution. The natural hardware/software co-design environment allowed us to manipulate the device from the perspective of the software engineer, where the hardware was merely a function call from the SW application program. The software engineer could debug his or her code using its standard environment, while also leveraging the HDL code directly as the hardware engineers produced it, in a concurrent engineering manner.
With Systemsim, we were able to use the Co-Design CBlend technology to co-simulate the ISS, written in C, and the design modeled in Verilog. This provided a faster and easier way to interface than the traditional programmable language interface (PLI) approach for incorporating C-based IP. We used it for 99 percent of our functional verification tasks. We also used a traditional synthesis design flow, and combined static timing analysis and gate-level simulation with an older simulator for timing verification.
Our design environment works well for us. The use of Systemsim simplified and sped up the verification task. If Systemsim was not available, the length of the verification cycle could have caused a significant issue for our overall time-to-market for the DSP core.
We are already into the next design phase and will continue the development of the processor. Our first customer completed a successful tapeout last year, sampled silicon earlier this year and is now in full volume production.
We do not plan to make any radical changes to the methodology. It worked well on our first design, and we will use a similar methodology for our next product family, which will be a multiprocessor DSP solution. For IP design where a C model must be verified against an HDL circuit, and the verification testbench is complex, this tool set provides a fast, powerful and easy-to-use alternative to other existing techniques and tool sets.