Understanding the power consumption of a chip design prior to its fabrication is no longer an option; it is a requirement. For engineering teams designing chips for the mobile market, the modeling and analysis of leakage power is particularly critical. The success of these products in the marketplace will be directly impacted by how well the engineering team manages the leakage problem. Accurate leakage models and detailed power analysis during the design phase are the keys to gaining the competitive advantage.
Power consumption has become a critical design specification, especially for today's system-on-chip (SoC) design teams. In the past, designers have either ignored power altogether or focused solely on dynamic power consumption. However, today many applications spend a majority of time in standby or quiescent modes, and in those modes, leakage power can dominate total power consumption.
Integrated-circuit power consumption has two primary components: dynamic power and static power. Dynamic power is the power consumed when circuits and signals transition between logic states, and thus is consumed only when the circuit is active and nodes toggle.
Static power, by contrast, is consumed even when the IC is inactive, and it is independent of any circuit or nodal activity. There are two types of static power, which are categorized by different types of current flow. The first type results from through currents that flow because of the use of current sources and are common in analog circuits such as differential amplifiers, phase-locked loops and sense amps. The second type of static power is due to leakage that arises because of the nonideal switch behavior of transistors in the off state. Leakage currents occur in all CMOS transistors, although some types of circuit designs exhibit more transistor leakage than others.
There are several sources of leakage currents in a transistor, including reverse-bias-source or drain-diode currents, drain-to-source weak-inversion currents and tunneling currents. However, the net effect of the various leakage-current components is to create a current flow from the power supply to ground through the transistor, even though the transistor is logically in the off state.
Concerns about leakage power have arisen out of both technological progress and market demand. In the technology arena, the relentless thrust of Moore's Law has produced smaller and faster transistors. However, a by-product of being smaller and faster is that transistor behavior has become less ideal in terms of functioning as a switch: The transistors are harder to turn off. Additionally, the reduction of supply voltages, driven by the need to reduce dynamic power, has resulted in much less voltage being available to drive the transistors into the off state. This problem will rapidly worsen as power supply voltages continue to decrease (see figure).
At the same time, the explosion in market demand for wireless, battery-powered products of all kinds has created a tremendous emphasis on battery life, which is largely determined by the leakage power in standby mode-the mode in which a portable system spends the majority of its time.
Several techniques exist for controlling and minimizing leakage power, involving both process and design technologies. The most prevalent process-oriented technique is the utilization of two different transistor threshold voltages (VT), which allows designers to use low-VT devices in the critical timing paths and high-VT devices (with lower leakage) everywhere else.
The option of a second threshold requires additional manufacturing steps, and thus additional cost. However, provided that accurate power models and analysis tools are used, this technique enables designers to minimize leakage power without affecting overall performance.
Design-related techniques include choosing cell-level circuit topologies based on minimum leakage, the utilization of a back-gate bias to dynamically alter transistor thresholds and gating the power to entire modules when those modules are inactive. While the first two design techniques are largely the domain of transistor circuit designers, the latter is the concern of logic and physical designers.
Nonetheless, all of these techniques, both process and design oriented, share the requirement for accurate modeling and analysis tools. Without them, designers are forced to guess about both the severity of the leakage problem and the effectiveness of various mitigation techniques.
Analyzing and controlling leakage power requires both accurate models of electrical-circuit behavior and tools that can interpret those models in the proper context. Traditional modeling techniques reduce all leakage measurements into a single average number, but these simple models have proven to be highly inaccurate and inhibit designers' efforts to analyze and reduce leakage. Thus, to deal with today's advanced processes and complex devices, more sophisticated characterization and modeling methods are required to represent the supply voltage, junction temperature and state dependencies.
Designers need to be cognizant of available expertise and tools for dealing with power leakage in SoC devices.
For its part, Silicon Metrics has significant expertise in understanding the nuances of power dissipation within an integrated circuit. It provides tools, such as SiliconSmart CR-PCX, that design teams can use to analyze and understand the effects of power dissipation in their designs.
Meanwhile, Sequence Design has focused on providing designers with the most advanced power-estimation and optimization capabilities. Tools such as Sequence's PowerTheater make it possible to reduce both dynamic and static power through extensive analysis and debugging facilities.
Stephen King is director of engineering at Silicon Metrics Corp. (Austin, Texas), a provider of deep-submicron characterization tools. Jerry Frenkil is vice president of low-power technology at Sequence Design Inc. (Santa Clara, Calif.), a design-closure solutions company.
© 2001 CMP Media LLC.
12/1/01, Issue # 13150, page 12.