The SOC designer's world is made up of two distinct groups-the logic, or system-level, designers and the physical-layout designers. Logic designers work on functional and timing issues, and physical designers address layout concerns. The conventional link between those two realms is through a series of models generated from a detailed and exhaustive set of tools to represent real silicon performance and enable designers to predict it. As feature sizes decrease, second- and third-order modeling effects take on increasing importance in modeling accuracy. Together with the increasing complexity of system-on-chip designs and experts-only EDA tools, time-to-tapeout is becoming an important factor for any COT (customer-owned tool) user. This article details the approach that 1st Silicon and Virtual IP Group used to validate a COT flow from beginning to end, complete with working silicon.
Designers often invoke the aphorism, "Live by the model, die by the model," and that held true for 1st Silicon and Virtual IP Group. A successful chip is highly dependent on the models used in implementing the process and the design. Once the COT flow and the models are validated, subsequent designers can realize a significant reduction in time-to-tapeout.
A semiconductor process is represented by a set of process and device models. Based on those models, the cell library and technology information are prepared. In the SoC designer's realm, the library and technology information represent all the intricacies and complexities of the semiconductor process (Fig. 1).
Designers are often faced with the question of the quality of the device models. The prerequisite to a reliable set of models is a qualified and stable semiconductor fabrication process. There are many steps that contribute toward establishing a qualified process. The SoC designer or COT user does not need to validate each of these steps before selecting a foundry or process, but adequate knowledge of them will enable the COT user to make intelligent choices.
It is useful to create a checklist to assist in verifying how key elements of the process conform to standards. After going through this checklist (Table 1, page 26), the COT user will have a sufficient level of assurance that the process and device models are built on a solid foundation.
The construction analysis of a semiconductor process starts with taking scanning electron microscope pictures of the silicon. Structural abnormalities, if any, are analyzed and problems resolved. In the wafer-level reliability tests, a host of tests are done on electromigration, stress migration, hot-carrier injection, gate oxide integrity, time-dependent dielectric breakdown, ionic contamination, threshold-voltage stability and other conditions. In packaged-product qualification, a product is taken through the steps of early-life, long-term-life, temperature-cycling and temperature-humidity bias tests. Failures from any one of these tests need to be sufficiently addressed by the proper quality- and reliability-assurance procedures, including return-material procedures and corrective-action reports.
In the modeling of the semiconductor process, much analysis is performed on the p and n transistors. Well isolation, device drive current, threshold voltage (Vt), device reliability, interconnect thickness and conductivity are just a few examples of parameters and silicon characteristics that are measured, verified and modeled into industry-standard descriptions. Any inaccuracies in translating the device properties to the simulation models will adversely affect COT design success. The wafer foundry is expected to supply a set of accurately extracted device models for circuit simulation and library characterization.
The Spice models for the transistors are extracted from wafers that exhibit the typical electrical and process characteristic. Accurate extraction and optimization algorithms of the model-extraction tools are fully utilized for I-V and C-V curve fitting to optimize the models for the linear, saturation and subthreshold regions.
The models are simulated and verified on silicon to validate key ac and dc parameters of the transistors and to ensure the robustness and quality of the models for first-silicon success.
Based on these electrical, process and device models, the library of standard cells, I/O cells and memory compilers is created and characterized for various process corners, temperatures and voltages. Each process-specific component is finely tuned to optimize for area, performance and power. A set of design kits, including technology files and EDA environment files, is generated together with the library and is verified through a meticulous qualification procedure using industry-standard techniques. After an exhaustive process of silicon verification, the library is complemented with a set of physical-verification (DRC) checks to ensure manufacturability.
To ensure consistency and repeatability of high yields, the process and device characteristics are monitored and verified continuously. Hundreds of device parameters are measured at the outgoing E-test parameters check. A handful of important parameters, such as threshold voltage, IDRV and BVDSS, is reviewed by analyzing the Cp and Cpk information together with their specification limits. Cp trends show the tightness of the data distribution; Cpk trends show whether there are skews to the high or low end of the specifications. The statistical process control method continuously monitors the controlled items of the process parameters to guarantee the stability and repeatability of the device's performance.
Constant monitoring of the device models and their effect on the library performance is a crucial step, taken to ensure that the library has sufficient margins for process variations. Library recharacterization will be required if the process models are changed or optimized for yield and performance improvement. Quarterly revalidation of the consistency, stability and margin study of the process is part of the typical device-model and library-verification procedure at 1st Silicon.
To verify the accuracy of the fundamental devices and other IP building blocks, Virtual IP Group partnered with 1st Silicon to validate a front-to-back design flow using 1st Silicon's foundry-specific cell library and third-party EDA point tools. The process began with the selection of three IP cores from Virtual IP Group's portfolio. The cores were meshed together at the register-transfer level so as to create a fully functional and testable chip design.
Since the intent was to emulate a typical and realistic design, the IP cores needed to have synchronous as well as asynchronous logic, various flavors of SRAMs and multiple clock domains. The IP cores selected were a microcontroller, a UART and a USB device controller. The USB controller was also instantiated a second time to act as the I/O peripheral interface for the microcontroller core. The combined design resulted in 11 instances of SRAMs with a total count of 50,000 bits, 42,300 gates of random logic, five clock domains and 17,787 nets.
The first step in the design flow was logic synthesis using the cell library and generation of a gate-level netlist. This step was uneventful, since each individual IP core had previously gone through such exercises many times. The pre-route SDF generation step involved the first variable selection point, since wire-load delays had to be generated. The user input to the design flow was the estimated core area. If the area estimated was optimistically small, the pre-route SDF delays would generally err on the low side, meaning the user would be led to believe the design worked at a higher performance level. If the area estimated was large, the reverse would be true. Designers consider the latter scenario, if not taken to excess, the preferred choice.
The object of the exercise is, then, to find out if the combination of the process technology, cell library and EDA tool would overpredict or underpredict at the pre-route timing-simulation and analysis phase of the design.
Before the place-and-route exercise, scan insertion and JTAG insertion will also add delays to the sequential elements of the design and further complicate the correlation between pre- and post-route timing. After placement and routing, the layout tool generated a post-route SDF delay file with the actual net delays calculated from the routing capacitances and resistances. The SDF delay file was used for post-route timing simulation and analysis. After experimenting with various block sizes and layout approaches, it was found that the pre-route SDF delay was consistently predicting timing that was too fast by 50 percent or more. If scan or JTAG insertion was included prior to place and route, the pre-route SDF delay would have been even more optimistic.
After several cycles of estimation and layout, it was found that the block area had to be exaggerated by 70 percent (80 percent for scan-inserted netlists) to compensate for the optimistic pre-route delays. That is an important finding, since it means designers need to take this "correction factor" into account on future designs and minimize the cycles needed for timing convergence (Fig. 2).
The place-and-route stage of the validation process necessitated various match-and-try exercises. The technology files prepared by the library vendors allow for user options such as stacking or nonstacking of vias. For diode insertion to minimize antenna effects, the layout engineer had to match different parameters with different layout tools and even with different versions of the same layout tool.
Another consideration was use of layer maps when user-generated custom blocks were imported to the layout. At the layout verification stage, DRC run sets took into consideration whether the top-metal rules, which are more relaxed, had to be applied to the third, fourth, fifth or sixth metal layers-whichever case the design required. The inclusion of LVS run sets for checking analog blocks and special geometries required additional debug and verification.
Once the various options were selected, the IP design test case was taken through to full-chip DRC/LVS/antenna checks. The results were then verified and confirmed. The layout team did not stop here. A set of Make Scripts was created and tested so that a multitude of future design options and combinations could be handled quickly, reducing time-to-tapeout for the layout team.
The tapeout phase also required careful consideration and verification. Tapeout documents have to be prepared to identify the die sizes, scribe and seal ring composition, bonding-die orientation mark, and location for E-test circuitry insertion.
At the end of the tapeout exercise, a complete checklist is prepared to facilitate future tapeouts. The intention here is to ensure that subsequent tapeouts will take a fraction of the time it took to tape out the IP test design.
For this validation exercise, 1st Silicon reported that key E-test parameters were 15 percent within the specification limits with the Cpk at 1.33. Looking at the Cp/Cpk trend for the previous six months, these parameters are within the control limit of the process. Furthermore, from the ring oscillator verification, the actual frequency measured on silicon is 5 percent faster than Spice simulation. That shows good correlation between device models, E-test and silicon. The library, which was characterized to be within 10 percent of accuracy of the device models, performed as specified.
During the design phase, several performance-measurement parameters were identified for purposes of silicon measurement. One parameter set is the input-to-output delays of several long delay paths. After the successful fabrication of the IP test design, the prototypes were evaluated and the delays measured.
E-test results showed that n-channel devices had 4 to 5 percent skew for higher performance but an 8 to 10 percent skew for lower performance for p-channel devices on that particular wafer, 1st Silicon reported. That information was taken into account in the evaluation process.
The results for input-to-output delay paths showed inconsistencies (Table 2). Most silicon-measured delay paths were faster than post-route predicted values, with one path showing up to 30 percent deviation (Port 2). Only one delay path showed close to 12 percent slower than post-route value (USB_Mode). The post-route SDF delays of the paths with the highest positive and negative deviations were analyzed. It was found that, with a tolerance of plus/minus 5 ns, most of the errors were due to bench-top measurement equipment accuracy. The SDF delay extraction methodology was sound and will produce working silicon with acceptable results in future designs.
Joseph Hong, executive vice president and a founder of Virtual IP Group (Sunnyvale, Calif.), held various positions at Amkor Technology, SiArc and S-MOS Systems. In 1995, he founded and sold Pacific Semiconductor Inc., a fabless ASIC supplier. Hong holds a BSEE and an MSCS from Stevens Institute of Technology (Hoboken, N.J.).
S.C. Sia is section manager of the application-engineering group at 1st Silicon (San Jose, Calif.), a Malaysia-based wafer foundry. Earlier, he was a staff engineer with Motorola Electronics (Singapore) Pte. Ltd. Sia holds a bachelor of engineering in electronics degree from the University of Southampton, U.K.
© 2001 CMP Media LLC.
12/1/01, Issue # 13150, page 16.