Designers agree that they must address signal integrity when using a 0.13-micron process or below. But less clear is just how and where in the design flow signal integrity should be dealt with. Even though there are now various EDA tools that allow designers to improve design noise immunity such as its ability to function and perform as expected in the electrically turbulent environment of nanometer process technologies it is not always obvious where and when to deploy those tools.
All solutions to signal integrity problems involve design trade-offs in terms of design productivity, performance, power, cost, yield and reliability. In some cases a signal integrity solution is overkill and results in unnecessary design iterations. In other cases, it is even more catastrophic: The solution misses a critical problem that requires a costly silicon re-spin to resolve. The key to designing successfully in 0.13 micron or below is to develop a comprehensive signal integrity methodology so that the correct trade-offs to manage signal integrity are made at each step of the design process.
No single methodology is the correct approach for all designs. In determining the one to use, it is important to understand the choices available and to tune your methodology based on your design's market requirements.
For example, in a graphics chip a signal integrity error that sometimes causes a few pixels to be displayed incorrectly may be tolerable, but a flaw in the arithmetic unit of a microprocessor would not be. In addition, the volume of the end product and the market window can play an important role in selecting the signal integrity methodology. For example, high-volume parts are cost sensitive, so any unnecessary overdesign to remove signal integrity problems will hurt the bottom line.
Another important step in defining a signal integrity methodology involves selecting the noise sources that must be managed and those that can be safely ignored or designed out. This is a function of design style, process technology, clock frequency and, once again, market needs. For the majority of standard cell-based digital designs, the important noise sources to manage are voltage (IR) drop (or fluctuations in the power supply) and crosstalk (interference between adjacent signal lines).
However, before deciding to ignore certain noise sources, safeguards must be put in place to ensure that these assumptions are valid. For example, if charge-sharing noise (noise created by the redistribution of charge when a signal is not being actively driven) is not being considered, then the use of dynamic logic should be prohibited or severely limited. Creating design restrictions that minimize or eliminate certain noise sources before implementation will greatly enhance design productivity but it typically comes at the expense of performance and area.
Though signal integrity problems arise due to the electrical interactions created by a chip's final physical design implementation, some design choices can be made in the early chip-planning phase that can help create noise-immune designs. Chips are typically created from a mixture of existing cores, macros, standard cells and newly designed blocks. For each predesigned subcomponent, an out-of-context analysis can be performed to determine whether the component is potentially noise sensitive, a major noise source or both. Knowing this information up front can help determine the correct strategy for utilizing that component within the design.
For example, being able to route over the core will save valuable routing channels, permitting a more optimal design. The risks involved in routing over hard IP can be quantified easily: Create a worst-case analysis over the block routes and analyze the underlying core with a transistor-level static noise analyzer. From this worst-case analysis, decisions can be made regarding the noise-prevention technique to use for this core.
Similar types of early analysis can be performed for all known blocks such as memories, standard cells and I/Os. If a block is a potential noise source, then various techniques can be used to minimize its impact on its neighboring circuitry, such as adding guard rings, spacing, shielding or selecting a different implementation of the same function.
Special attention should be paid to key chip-level signals like power buses, clocks, chip-level routes (especially buses) and even reset, enable and scan lines. Power buses have to be wide enough to minimize voltage drop but not so wide that they waste valuable chip area. It is very difficult to repair the power routing after the design is assembled, so early work using worst-case estimates of switching behavior and power consumption should be used to safeguard against excessive voltage drop. For this early analysis, an IR drop tolerance for the chip can be determined and used as a generic bound for all the remaining design implementation and analysis tasks. As the implementation of the design progresses this bound can be relaxed.
Clocks are very sensitive to signal integrity, particularly crosstalk. Crosstalk on a clock cannot only cause changes in clock delays resulting in unwanted skew, but it can also cause functional violations due to "double clocking" or false triggering of flip-flops or latches. Double clocking can occur when crosstalk causes a clock to cross its switching threshold more than once during a single transition. Only a small amount of crosstalk is required to create a double transition if the noise glitch occurs just as the clock's active edge is reaching its trip point.
Double clocking can be particularly troublesome for counters, state machines and on-chip clock dividers, which rely on the fidelity of the clock signal. In addition, clocks can be major noise sources, as they are high-speed switching signals that traverse much of the chip. The simplest solution to these problems is to shield the clock so that it is neither a crosstalk victim nor crosstalk aggressor. The complete clock signal or critical portions of the clock can be shielded. In addition, the use of gated clocks where certain clocks and associated logic can be deactivated during certain chip operations will not only help reduce power but also help improve signal integrity by reducing unnecessary switching.
Reset, enable and scan lines are typically not given much design attention as they are not timing critical. However, for the same reason they will tend to be weakly driven long lines with many fast switching neighbors and, consequently, be likely crosstalk victims. If a significant crosstalk glitch occurs on the reset line, the likely outcome is an asynchronous reset and a functional design failure. Similarly, scan signals are also vulnerable to crosstalk.
Major chip-level buses typically need special attention because they tend to consist of multiple wires routed adjacently on the same metal layer. A number of techniques can be used to manage signal integrity on buses, including the use of wide wire widths; wider spacing between wires; repeaters to break up wire lengths; different routing layers for adjacent wires; interleaving power and ground lines at regular intervals amongst the bus signals, or using specialized design knowledge to control the order in which the buses' bits are routed.
For very high-speed buses, inductive coupling effects may need to be analyzed. This is very challenging, time consuming and costly. One alternative is to determine the design parameters under which inductive effects can be ignored and adjust the design accordingly. For example, inductance can be ignored on short wires (due to fast slew rates) and long wires (due to being resistance dominated) where the values for long and short can be calculated based on expected slew rates and process parameters. By enforcing all wires to be either short or long the need for inductance extraction and analysis can be eliminated.
All the signal integrity methodology choices can be made early. They all involve tradeoffs in terms of area, performance and engineering schedule. They can be implemented through design methodology restrictions or by using tools that will enforce the decisions in a correct-by-construction fashion.
Managing signal integrity
Physical implementation for large designs is typically a two-step process. The first involves creating a full-chip physical prototype or floor plan; the second involves detailed block implementation. How much signal integrity prevention can be used in this early phase is a function of how close the initial plan or prototype correlates to the final physical implementation. If wire layers and routing tracks are not known, then any signal integrity analysis at this phase is probably wasted and may hurt rather than help. However, if the prototype bears a close resemblance to the final routing, early analysis can pinpoint potential problems and save wasted iterations in the detailed block implementation.
Most block implementation tools support options for reducing signal integrity during placement and routing. In the placement phase, for example, weakly driven nets can be identified and upsized to improve their noise immunity. Other prevention techniques are to restrict the routing length of adjacent signals to a certain distance, or to use switching times of signals so that adjacent signals do not switch simultaneously. Often, the design determines how effective these prevention heuristics are. For example, using switching times of signals will not be effective in designs that use many asynchronous clocks.
Also becoming available are routers that analyze and correct for signal integrity problems as they route. As noise immunity is dominated mostly by interconnect effects, this is a logical place in the design flow to focus on signal integrity prevention.
Block verification of signal integrity involves performing a detailed 3-D extraction and signal integrity analysis of final layout. This should be done on each block as it is completed so that repairs can be made prior to chip assembly. The output from block-level signal integrity analysis should be a list of potential failures and a list of fixes to automate the repair of those failures.
What is deemed a signal integrity failure is very tool-dependent a true failure is one that causes a problem in silicon. However, in order to safeguard against costly silicon failure, all signal integrity analysis tools take a pessimistic view. They will try to determine the worst possible combination of plausible noise events that could potentially happen on every net and will check the aggregate of these events against some predefined failure criteria. There is pessimism in both the noise calculation and the failure criteria. The worst-case noise combination may not occur because of the timing and logical relationships of signals and, furthermore, the failure criteria may be overly conservative.
The important thing to remember is that signal integrity analysis tools will report false failures and some tools are a lot better than others at filtering these failures. If you do not have a tool to filter these false alarms, then there are two options: apply design resources to examine each failure in detail or blindly fix the false violations. The former is very design intensive while the later can cause so much churn to the design that the fix-and-repair process will never converge. The fixes that can be automated include inserting repeaters on victim wires or upsizing victim drivers to better defend against attacks. Other techniques include spacing wires, shielding wires, widening wires or rerouting wires.
Once the final chip is assembled and before tapeout, the design should go through final signal integrity sign-off to validate that the completed design would function and perform as expected. Full-chip validation can be performed either hierarchically using abstract block-based signal integrity models, or it can be done flat. The later approach takes longer but accounts for the subtle interactions between chip-level routes and the overlying blocks. The former is faster, but it is harder to manage. The final signal integrity sign-off analysis should not only be thorough and accurate, but able to handle full-chip capacity with full-chip elements such as I/Os, analog blocks, IP cores and memories, as well as standard cell elements.
For 0.13 micron or below designs, signal integrity must be addressed. Getting the most out of signal integrity tools involves creating a methodology that comprehends the trade-offs involved at each design step. Understanding the market requirements of your design is key to creating the correct signal integrity methodology for your chip. With the correct combination of tools, methodology and expertise, signal integrity can be managed without compromising other design goals like timing, area or product schedule.