Accelerant Networks is a developer of high-integration ICs that allow rapid development of intelligent, high-speed backplane connection systems. To avoid signal integrity problems, the Accelerant design team needed a powerful verification methodology able to handle detailed simulations of a largely analog/mixed-signal design. Drawing on a combination of commercial and proprietary tools, the Accelerant team developed an effective mixed-signal verification flow, using full-chip, transistor-level, post-layout analysis.
The emergence of higher bandwidth applications brings increased demands for a more reliable, higher speed data communications infrastructure. At the heart of this infrastructure, backplane electronics for networking equipment face one of the most challenging operating environments in the communications industry.
High-frequency signals must run reliably amid a variety of noise sources. As a further complication, these signals face demanding line conditions that have traditionally required careful tuning during design to avoid signal degradation from line reflections and crosstalk. In fact, the operating conditions can change at any time as technicians move cards to meet new application requirements, requiring additional tuning in the field to maintain an optimal signal environment.
As companies look to support data throughput rates beyond 1 Gbit/second, traditional signaling methods break down. At gigahertz levels, signals face severe attenuation in long signal traces in common printed-circuit board (PCB) materials such as FR4. As a result, manufacturers compromise performance or select more expensive exotic materials.
Although designers have been able to tune signal traces and transmitters to deal with these problems in 1 GHz designs, the move to even higher speed systems beyond 3 GHz requires designers to adjust every transmitter and PCB trace.
Accelerant Networks' signaling technology allows transceivers to operate in a backplane environment over copper on standard FR4 materials. At the heart of this new approach, multilevel analog signaling methods permit transmission of two data bits per clock boosting data throughput while lowering the observed transmission rate. Deployed in new full-custom designs such as the Accelerant Networks AN5000, this type of signaling technology enables 5 Gbits/s bandwidth per differential pair using standard connectors and dielectric material for distances up to 48 inches.
In delivering these benefits, this type of backplane IC presents a significant design challenge, requiring careful attention to key timing, performance, power and signal integrity issues. In this case of the AN5000, the full-custom mixed-signal design was targeted for a robust 0.25-micron CMOS process from Taiwan Semiconductor Manufacturing Co. (TSMC).
With gigahertz clock rates, however, this type of circuit pushes the limits of that process technology with a variety of high-speed signals and complex clocking schemes. In turn, this type of design demands particularly thorough simulation to ensure power and signal integrity. Accordingly, one of our primary objectives focused on deploying a robust verification methodology that not only provides the required high levels of accuracy but also delivers high performance simulation execution and capacity for comprehensive post-layout analysis.
Full-custom design flow
Accelerant's overall design flow for this type of full-custom mixed-signal design comprises a combination of commercial and in-house tools. The full-custom flow starts with Analog Artist from Cadence Design Systems (San Jose, Calif.) for design capture, followed by Cadence's Spectre Spice simulation for handling analog analysis and Spectre-RF for detailed RF analysis. Detailed analysis used Spice models of the die and package interconnect developed using the 3D High-Frequency Structure Simulator (HFSS) from Ansoft Corp. (Pittsburgh, Pa.) for electromagnetic field simulations.
Following full-custom physical design, the design flow generates netlists that are particularly complex because we perform full RCLK extractions for post-layout analysis. For this approach, we developed our own methodology for parasitic extraction, combining xCalibre from Mentor Graphics Corp. (Beaverton, Ore.) with internal tools for inductance extraction and resistance-capacitance (RC) reduction from the full-custom physical layouts. Given this flow, the remaining issue is determining the optimum approach for verification.
Concerns about performance, power and signal integrity translate into a diverse range of verification requirements. Verification of all circuit blocks in this type of design is difficult because these designs are essentially analog in nature, and they are fairly large and complex at that. Nevertheless, a robust verification method is critical for a design team to verify dynamic timing and functionality at both pre-layout and post-layout stages. Using estimated parasitics, pre-layout analysis offers data needed to understand design performance, but the availability of accurate post-layout parasitics provides the detail required to uncover potential signal integrity issues.
In this approach, Spice-level accuracy is essential. Yet, we face the familiar problem that our resulting netlists are too large to run in a conventional Spice simulator, particularly for post-layout analysis when back-annotation of parasitics significantly increases the size of data sets. Additionally, communication channel designs require extremely long simulation runs. Traditional Spice circuit simulators can only handle small partitions or subcircuits running for a small number of cycles. Longer simulations are of course possible, but can take weeks to complete.
Because of these considerations, we originally initiated design of the AN5000 using a traditional mixed-mode simulation approach because of its potential for providing detailed results for subcircuits. Mixed-model simulation combines transistor-level simulation for critical paths with more abstract models for other design blocks. Here, we ran a mixed Verilog/Spice-type simulation, using transistor-level Spice-type simulations for critical paths and subcircuits and analog behavioral models running in Verilog for other blocks.
In principle, this approach would be considered a reasonable compromise for providing detailed results within a reasonable time. In practice, however, we found that the mixed-mode approach grows increasingly cumbersome as design proceeds. As we started to verify substantial portions of the AN5000 design, we found that the task of building suitable analog behavior models began to slow the design flow. Indeed, this approach requires a design team to maintain essentially a parallel development effort to ensure consistency between the transistor-level design and analog behavioral-level models.
Due to the increasing difficulties with this mixed-mode approach, we turned instead to a newer verification method based on chip-scale circuit simulation. Newer tools like the HSIM circuit simulator from Nassda Corp. (Santa Clara, Calif.) offer Spice-level accuracy, but also provide the capacity and simulation performance needed to conduct chip-scale simulations in a relatively short amount of time. After we confirmed the accuracy of this approach, we abandoned the earlier mixed-mode simulation approach.
With the AN5000 design effort, we found we can move the entire design as a Spice netlist into HSIM (hierarchical circuit simulator) and perform full-chip simulations at full transistor-level accuracy. By simulating the large circuits at the transistor level, we can tune individual subcircuits with confidence not only in the accuracy of the target subcircuits but also in the accuracy of the remaining blocks. The final check in the Accelerant verification flow involves a comparison between pre-layout and post-layout results. By quantizing the post-layout analog waveforms to digital, we are able to compare those results with the Verilog digital output using timing window functions. This final step provides a critical check on timing of the interfaces.
By their very nature, the post-layout HSIM simulations exhibit the effects of on-die signal integrity issues on dynamic timing. This is absolutely critical when routing large numbers of unrelated RF speed signals around the die.
Our verification approach allows us to verify critical performance parameters, including clock skew and margin checking for setup and hold times. Furthermore, the ability to perform simulations of large blocks for many cycles allows us to verify long-duration events including settling performance of phase-lock loops. For the AN5000 design, this approach proved critical for closing timing on the block communications and mixed-signal interface. Because these simulations complete rapidly, we are able to run the thousands of simulations needed to verify and characterize critical performance parameters.
The ability to complete very large simulations at the transistor level is becoming increasingly important for the type of complexity inherent in the AN5000. For this design, we were actually able to verify performance by simulating the entire post-layout clock recovery circuit for 8 microseconds of simulated operation. Due to its very nature, a true full-chip simulation of the AN5000 would require trillions of simulation cycles. We were however, able to bring up the entire circuit long enough to verify the internal connections a task that would have been impossible with traditional verification methods.
The high-speed 130,000-transistor (mostly analog) mixed-signal design of the AN5000 is the first of its kind in providing multi-gigabit data rates at significantly lower observed transmission rates. Because the Accelerant verification methodology can thoroughly verify the design and exhaustively characterize its performance with real-world signals, Accelerant achieved first-silicon success a significant advantage in a competitive market. In retrospect, the ability to handle the entire Spice netlist proved to be a key and vital element in this achievement, because it enabled a level of comprehensive verification that provided the Accelerant team with greater confidence in moving to tapeout.