With process technologies evolving from 0.18 micron to 0.13 micron and on to 90 nanometers, signal integrity effects are strongly influencing the performance of integrated circuits. Two of the key ones are noise and delay due to cross-coupling capacitance. Noise may cause functional failures; delay may result in timing violations. It is now common for the slack of the critical paths of ASIC designs to degrade by as much as 400 ps due to crosstalk. This is significant for designs running faster than 400 MHz.
When a signal switches, it may affect the voltage waveform of a neighboring net. The switching net is typically identified as the "aggressor" and the affected net is the "victim."
Crosstalk can impair both timing and functionality. When the victim net is quiescent, crosstalk can result in a noise-induced functional failure when the noise is propagated to the input of a register (latch or flip-flop) and changes the state of the latch.
When the switching windows of the aggressor and victim nets overlap and the nets switch in opposite directions, crosstalk will increase the delay of the victim net, which may result in setup violations. When the nets switch in the same directions, crosstalk will reduce the delay of the victim net, which may result in hold violations.
A crosstalk-aware timing analysis tool is needed to assess the crosstalk effect. To model the effect accurately, the switching directions and the switching times are needed. In addition, the strength of the driver gates and the distributed cross-coupled RC modeling of the interconnect are also important. This analysis is typically performed when the layout of the designed is finished, after detailed routing.
Historically, crosstalk delay problems could only be fixed after detailed routing with a series of engineering change orders, the familiar ECOs. Typical methods included buffer insertion, cell resizing, track reassignment of the victim nets and additional wire spacing allocated to victim nets. Cell resizing can be very effective since the replacement of cells has a localized effect on the layout and will require only reconnection of the signals to the equivalent pins.
Inserting a buffer can be difficult since its addition can introduce additional delay and may result in a timing violation in the critical path. Buffer insertion can also increase power consumption. Track reassignment moving a wire from one routing track to a different one can solve the identified crosstalk problem. However, this may introduce new crosstalk effects on other nets and create new critical paths. Also, the ECO process assumes that there are enough routing resources to accommodate the fix and that is not always true.
Global routing's role
For the crosstalk ECO flow to be effective, enough routing resources must be available, which means that crosstalk prediction must be built into the global router. Any effective solution to address crosstalk problems must include crosstalk prediction and avoidance, and then repair for those paths on which avoidance was unsuccessful.
At the global routing stage, the crosstalk delay effect on the timing of the critical paths can be estimated. This requires a crosstalk-aware static timing analysis tool for globally routed nets. The difficulty is in the extraction of cross-coupling capacitance when the signals are not yet detail routed. Prediction of crosstalk effects can be quite accurate if the layers and routing tracks are assigned to the signal nets during global routing.
However, current routing technology is not mature enough to guarantee that a detailed router can precisely follow the layer and routing track assignments set by the global router and still complete the connections cleanly. This limitation is common for high-performance designs when routing resources are limited, particularly if the detailed router has a gridless mode for variable wire widths and spacing. When the detailed router does not follow the routing guidelines from the global router, the crosstalk analysis and the associated timing estimation is not useful.
A practical approach is for the global router to assign signal nets to layers and to global routing cell (GCell) edges based on the available routing resources for each layer. The detailed router will then follow and complete the connections without causing design rule check violations. Using a statistical approach, the coupling effect on each net can be estimated and the static timing analyzer can determine which nets are in the critical paths. Once the crosstalk-critical nets have been identified, additional routing resources can be allocated so that the crosstalk avoidance flow can be implemented with the detailed router.
Using wire spacing
Once crosstalk can be predicted during global routing, action to avoid crosstalk can be taken: A very effective means is wire spacing. If the spacing around a net is doubled, the crosstalk effect on a victim net can be reduced by as much as 46 percent. The crosstalk effect can be reduced by 75 percent when the equivalent of a routing track is left unoccupied on both sides of the victim net.
Crosstalk delay avoidance can be implemented during global routing. The crosstalk-aware static timing analyzer first identifies the critical paths and the crosstalk-sensitive nets within these paths. The crosstalk-sensitive nets are allocated extra spacing during the global routing stage so that the crosstalk-induced delay can be reduced.
Since routing resources are typically quite limited, the challenge is to ensure that no additional geometric design rule check violations are created during detailed routing. The additional spacing assigned during global routing is a secondary requirement. Spacing requirements specified by the process design rules have top priority since they are hard manufacturing requirements. Therefore, the detailed router has to implement rule priorities so that the process design rules for spacing are followed before assigning additional crosstalk spacing around the specified nets.
For each signal net, there may be many aggressor nets. Detailed circuit analysis for each net with all the aggressor nets may consume an unacceptable amount of time and computing resources. It is common for the crosstalk noise analysis tool to sum up peak noise estimates from all aggressor nets and apply the total to each victim net. However, the result can be overly pessimistic since the aggressor signals do not typically switch at the same time.
The crosstalk analysis tool can model each of the aggressor signals as a triangular waveform and determine the peak noise based on a composite of these waveforms. An effective means of dealing with crosstalk noise is to assign additional spacing to the victim net whose peak noise and waveform width is above the acceptable threshold for the input of the cell to which it is connected. The threshold values are determined through cell characterization by the ASIC vendor or the cell library provider. The accuracy of this simple method is typically adequate as a screening mechanism to identify the victim nets.
Since crosstalk noise is not a problem unless it is propagated to the input of a latch and causes a functional failure, the above approach is quite conservative. The number of sensitive nets that must receive additional spacing can be significantly reduced with a more comprehensive analysis method and a noise propagation model for each of the cells in the library. The noise propagation model will define the peak and width of the output waveform based on the input waveform. If the peak and width of the input waveform is less than a value specified within the model, then the noise will not be propagated beyond that cell.
Any propagated noise will then be added to the crosstalk noise waveforms for each net and further propagated downstream until the input pin of a register (flip-flop or latch) is encountered. If the accumulated noise is above the threshold for the input pin of the register, then it will cause a state change resulting in a functional failure. To prevent this, all nets from the source of the noise to the register input are assigned additional crosstalk spacing. The same crosstalk avoidance flow that is used for delay is also applicable for noise avoidance.
If cells are placed using a min-cut, quadrisectioning or similar algorithm, the ideal crosstalk avoidance solution is to assign routing resources during global placement. Once the cells are assigned to a global placement region or bin, a global router can determine the connections that cross the global routing cell (GCell) edges. Typically, the global placement bins are the same as the GCells. The placement of the logic cells can be modeled to be located at the center of the bin.
During global placement, the bins and GCells are very large, so there can be many nets crossing each GCell edge. There are significant timing uncertainties because, at a coarse level of granularity, critical paths are modeled abstractly as a collection of routing connections through Gcell edges. A statistical method can be used to model the crosstalk effect of the aggressor nets on a victim net. The signal switching windows are used to assess the crosstalk interaction between signals. A switching window density histogram can then be constructed and then used to identify the crosstalk noise and delay impact on each signal net.
The nets that have switching times within windows of high switching densities will be assigned extra spacing. The accumulated spacing for crosstalk effects will be added to the routing congestion value for each GCell edge. The assignment and movement of cells to each bin will be adjusted so that the overall congestion (including crosstalk congestion) is well balanced among all the GCell edges. This will cause regions of high crosstalk congestion to be sparsely populated with logic cells and interconnect. As the bin sizes are progressively refined, congestion is further localized and more routing resources are allocated to the GCell edges with high crosstalk congestion. This will serve to ensure that there are adequate routing resources available when it is time to perform the final detailed routing.
As process technologies advance below 100 nm, the effects of coupling capacitance on functionality and timing will continue to grow in significance. Addressing these matters as early in the process as possible presents the best solution to achieving design closure in a timely manner. In this way, crosstalk avoidance can be incorporated into the construction of the design and not dealt with as an iterative and time-consuming post-processing operation.