Achieving Gigabit data rates is a challenge that can excite the imagination of chip designers. An equally significant challenge is making these designs testable, but somehow designers don't get excited about test.
Yet, because testing can be a substantial portion of a chip's production cost, test strategies are an important part of high-speed circuit design. For example, in NurLogic's HyperTransport physical-layer interface (PHY) core, that meant taking specific steps to increase fault coverage while minimizing test time and cost.
Basically, the HyperTransport protocol is an emerging approach to solving the challenges of achieving high-bandwidth data transfers while avoiding circuit design and integration complications of clock/data recovery schemes. This is achieved by maximizing a source synchronous interface throughput up to 1.6 Gbit/second and further increasing the bus width.
The I/O interface of the HyperTransport PHY is comprised of 2 to 16 bits of receive and transmit buses operating at 1.6 Gbit/second for an aggregated full duplex rate of 25.6 Gbit /second. Associated with every eight bits of transmit data is a control signal indicating the status of the data on the bus. A single-phase delayed clock is used for source synchronization of up to 16 bits. The transmitted source synchronous clock is used on the receive side to capture the data and control bits.
In order to allow the system to operate at 1.6 Gbit/second, detailed attention is paid to the link budgets at the ASIC level as well as the board and package level. To maximize I/O performance at 1.6 Gbit/second, differential signaling with specific electrical characteristics are used. Also, integrated in the IP is a calibration circuit, which is dynamically run in the background to provide the proper impedance matching, hence minimizing return loss.
NurLogic's HyperTransport PHY core, serializes a 64-bit data bus and an 8-bit control bus operating at 200 MHz, down to an 8-bit data bus and a 1- bit control bus on the transmit side using an integrated PLL for clock multiplication and de-skewing. On the receive side, captured 8-bit data input along with the control signal is de-serialized to a 64- bit data bus and an 8 bit control bus, respectively, using the received source synchronous clock, and further re-synchronized to the internal system clock operating at 200 MHz. The design is fully compatible with the commercially available tunnel, bridge, host and cave cores.
However, integrating the HyperTransport PHY into a design introduces many challenges. With as many as 38 I/Os (data, control, and clock) running at 1.6 Gbit/second and greater than 145 internal signals running at 200 MHz, independent validation of the PHY macro becomes an important factor. Production testing of the I/O interface and validating the performance of the HyperTransport PHY is a problem that cannot easily be addressed.
NurLogic's engineers wanted the PHY core design to accommodate production test requirements by minimizing the need for the tester to handle these troublesome situations. Many design considerations have been given to allow for independent at-speed testing of the PHY core using conventional automatic test equipment.
To maximize test coverage utilizing conventional design for test methodologies, the 200 MHz signals are up converted to 1.6 Gbit/second signals on the output side and reciprocally down converted on the input at the I/O interface block. This results in the majority of the internal signals operating at 200 MHz, allowing for scan insertion and achieving greater than 80% functional fault coverage. Serial and parallel loop-backs along with BIST logic are implemented to further enhance fault coverage and allow for at-speed testing of the core. Furthermore, all I/Os are JTAG enabled allowing for board level interconnect test. Implementation of AC JTAG will be available in future revisions of this core.
The PHY core's BIST circuit eliminates the need for high-speed test during production testing. It is able to drive the control output line as well as the serializer's parallel inputs, and then compares them with the deserializer's parallel outputs at full data speeds. The BIST circuit flags any errors in the received signals, providing a pass/fail report to the tester. It will work either with internal loopback, which tests the digital logic, or external loopback, which tests the logic along with the I/O.
The BIST circuit has three modes of operation, corresponding to low-, medium-, and high-speed test requirements. At low speed, the BIST generates a pattern of 61consecutive zeros, followed by a toggle to one and back to zero, followed by another 61- bit stream of zeros. It can also generate the inverse pattern. These low-frequency patterns facilitate the testing of signal lines for stray capacitance, which would appear as signal-line charge-up that masks the single-bit toggle.
For medium-speed testing the BIST circuit provides a pseudo-random code generator using the polynomial x23+x18+1. The production tester can load the generator with a starting seed value, and then initiate the self-test. Once started, the generator runs until stopped, allowing control over the test duration. The generator will loop through all its possible bit patterns in 5.2 milliseconds when running at top speed.
As the test runs, the BIST circuit loads the generated patterns into the data serializer and the control line for conversion to serial bit streams. After a delay that accounts for the loopback path length which checks for specific patterns, the BIST compares the incoming parallel data with the loaded pattern and provides a pass/fail report. In the case of failure, the circuit also reports the seed used as well as the number of the cycles that failed.
This medium-speed test setting increases fault coverage for production testing without adding significantly to the tester's burden. It is also useful as a test generator for performing external measurements on the chip's performance. Measuring the eye pattern on the differential signal lines and characterizing channel-to-channel interactions and pattern sensitivity, for instance, can be performed using the test circuits as a signal generator.
To test the circuit at high speed, the BIST produces an alternating one-zero pattern on the serial lines. This checks the circuit's high-speed behavior and provides an opportunity for board designers to check for noise generation on the signal traces. Because all sixteen serial channels are running synchronously and each producing, in effect, an 800 MHz clock, this setting produces the interface's worst-case electro-magnetic interface (EMI) scenario.
While the loopback modes and BIST circuits help test the PHY's high-speed digital circuits, they only provide a stimulus for the analog sections of the chip's I/O lines. The analog section still requires external probing for parametric measurements. With regards to fault coverage, testers will need to infer circuit deficiencies from the bit error rates (BER) achieved in loopback testing or from other parametric measurements.
One parameter that doesn't need measuring, however, is the circuit impedance. NurLogic's engineers designed the PHY to include an I/O calibration circuit that allows the chip to match its I/O impedance to external reference resistors. The calibration occurs on demand or can be set to run continuously.
To design the calibration circuit, our designers took advantage of the internal consistency that integrated circuits demonstrate. For example, the calibration block has its own transmit and receive I/O circuits. These circuits are identical to those that connect off-chip, allowing the block to determine calibration coefficients that will apply to the other I/O circuits equally well.
The I/O blocks all include a digitally controlled impedance network. The register, at the bottom of the calibration block, drives the off-chip I/O. A state-machine-controlled counter drives the calibration block's reference I/O. The resistor network provides a 32- step resolution, resulting in 30% variability to account for process, voltage, and temperature variances.
The essence of the calibration process is to determine the correct setting for these impedance control networks. When activated, the calibration state machine begins a counter at 11111 and compares the signal voltage of the transmit I/O block with the reference voltage that an external RC network provides. If the comparisons don't match, the state machine decrements the counter and repeats the measurement until the voltages do match. The calibration block then stores the matching value and repeats the process using the receive I/O block. When both calibration values are ready, the state machine signals the core logic that calibration is complete. It is up to the core logic to update the I/O blocks with the new calibration parameters.
This impedance-calibration process eliminates the need for long and involved impedance characterization during production testing. As long as the chip's nominal I/O impedance is within range, the calibration circuits will allow the PHY core to accommodate normal temperature- and voltage-induced variations. The result is precision impedance control without test hassles.
With the calibration circuit eliminating the need for extensive impedance testing, and the loopback tests with BIST eliminating the need for high-speed testers, the HyperTransport PHY core keeps its test costs under control while achieving better than 95% fault coverage. Instead of triggering the high costs normally associated with Gigabit data rates, the core stays in line with most moderate-speed circuits of similar complexity. In addition, the use of loopback modes and BIST makes the PHY tests self-contained, simplifying the test designer's task even further.
While perhaps this is not as glamorous as designing Gigabit-rated digital and analog circuits, designing for test in this way is equally important to the success of an IP core like the HyperTransport PHY. Modularity, lowered production cost, and simplified testing all contribute to the core's appeal and its ultimate success as a design solution.