Software-defined radio (SDR) technology is undergoing a difficult birthing process. Some of the challenges are technical in nature and some are a function of the softening of the technology market, in particular the communications segment. Advances in analog-to-digital converter technology are still required to support the high-dynamic-range requirements of wideband-radio front ends that offer true multimode global operability.
Advances are also required in the area of configurable high-bandwidth analog signal processing for realizing the RF and IF stages of a radio. Microelectromechanical systems appear to be a promising technology for addressing in-system configurable analog signal processing. As this technology matures and is combined on a single platform with digital functionality, the ideal of a completely configurable radio will move closer to realization.
The significant computation demands of the SDR physical layer (PHY) have been largely satisfied by highly parallel signal-processing platforms realized using recent-generation FPGA technology. To complement the device technology, signal-processing intellectual-property (IP) libraries and design methodologies are taking on renewed roles to provide a solution to the challenges the software radio presents.
While field-programmable gate arrays take advantage of Moore's Law and other advanced process technology such as all-copper interconnect and low-k dielectric substrates to increase clock frequencies over time, their primary mechanism for supplying performance is completely different from the instruction-set architecture (ISA) approach. FPGAs exploit the large amount of parallelism inherent in most signal-processing algorithms. These devices can be viewed as a naturally parallel-processing engine that can take advantage of the rich parallelism in a soft-radio PHY.
Basically, the software radio PHY is a complex signal-processing system in which algorithmic and functional-level parallelism can be leveraged to realize a high-performance system that does not rely on raw speed for its performance. For example, the multiplier array could be used to implement space-time processing in a receiver, while at the functional level, multiple turbo convolutional decoders could be concurrently operating to support multiple users, each with a 2-Mbit/second data rate in a 3G environment.
In the pursuit of Moore's Law improvements in feature geometries, manufacturers have been making 60 percent more transistors available to circuit designers per area of silicon, compared with what was available a year earlier. In contrast, the ratio at which designers are able to utilize transistors in circuits of any given tier of complexity has only been increasing at a rate of 20 percent per year.
Part of the reason for this "design gap" is associated with performance supply and demand, but another aspect is related to methodology. Developing and verifying a sophisticated ASIC is becoming an increasingly complex, time-consuming and error-prone procedure.
Further, at a cost of $1 million to $2 million for mask sets, it is becoming prohibitively expensive. We are at a point in technology where ASIC development time lines can be in the order of years, and may even extend beyond the window of opportunity for the intended product.
FPGAs address the technical as well as business perspectives. Since FPGAs are off-the-shelf commodity items, companies can access state-of-the-art device technology, with minimal NRE, and quickly build and deploy customized systems, achieving very short time-to-market while simultaneously maximizing first-to-market revenue streams.
One approach to base transceiver station (BTS) implementation has been to employ a combination of ASIC and instruction-set architecture DSPs. The ASIC technology is typically used to address the significant arithmetic requirements of the radio front end-for example, digital downconversion and channelization filters to support multicarrier W-CDMA or cdma2000 standards. Those functions are beyond the capabilities of even state-of-the-art ISA DSPs.
Even though the ASICs used in this part of the system may offer some programmability, it is generally limited in nature and is certainly a departure from the intended philosophy of the fully configurable soft radio. The DSP processors might be used for certain baseband functions such as source encoding and decoding, like a CELP codec. There would also typically be RISC-processing resources to support the requirements of the higher levels in the protocol stack.
From a soft-radio perspective, the ASIC/processor combination is a poor partitioning from both a flexibility and efficiency perspective. In recent years FPGAs have experienced hypergrowth in terms of the arithmetic complexity and compute density (number of operations/unit area of FPGA) that can be achieved by current-generation devices. What types of signal-processing functions can be usefully realized by an FPGA?
Radio designers working with FPGA technology implement IF sampled receivers, channelizers of different varieties including classical digital down- and upconversion architectures, FFT-based polyphase transforms, multistage multirate polyphase decimators and interpolators, adaptive interference cancelers for DSSS channels, multiuser detection and rake receivers (including acquisition and tracking). More recently, FPGAs have been used to construct space-time processors for advanced smart-antenna systems. FPGAs are extremely adept and flexible at implementing fast Fourier transforms, and this functionality has been used to construct orthogonal frequency-division multiplexing modulators and demodulators.
FPGAs have also found extensive use in narrowband, bandwidth-efficient quadrature-amplitude modulation systems. In this environment they have been used to implement adaptive channel equalizers, all-digital timing-recovery circuits, carrier recovery loops, frequency-locked loops and fractional rate change filters. FPGAs are also extensively used for forward error correction in communication systems. For example, OC-3 155-Mbit/s Viterbi decoders, Reed-Solomon decoding at OC-192 10-Gbit/s data rates and interleavers (or deinterleavers) operating at clock frequencies greater than 200 MHz are all achievable with current-generation FPGAs.
Leveraging these types of trade-offs does not always mean that the engineering team has to construct the functional units from first principles. To facilitate rapid product development many signal-processing functions are available from the FPGA manufacturers themselves and from third-party IP suppliers.
One of the roadblocks to the widespread deployment of FPGA-based signal processing has been related to design methodology. In the past, FPGA-DSP design has required signal-processing and communication engineers to use tool flows and languages they typically are unfamiliar with. The introduction of tools like the Xilinx System Generator for DSP has gone a long way toward letting engineers work in the language of the problem.
The platform FPGA provides the opportunity for the radio architect to reinvent the system. Instead of having, say, a radio card that is responsible for the DSP heavy lifting at the front end of a soft-radio system, and then passing this partially processed data over a VME or PCI-X bus to a baseband processor, multiple functions could be integrated into one or a small number of platform FPGAs. For example, the compute-intensive tasks in the radio PHY could be implemented in the FPGA logic fabric, while more decision- and control-oriented tasks are run as embedded software on the Power PC. This embedded processor could even be used to run a Node B application protocol for a BTS or a Java virtual machine, or could even provide Corba support.
One of the driving objectives underlying SDR concepts is the desire to have a single hardware platform that has the capability to service a number of radio environments. This type of reconfigurability could be used in several ways. For example, from the perspective of a manufacturer developing infrastructure equipment or a network operator looking to build out a network, a soft radio system could be deployed in Europe and configured to support, say, UMTS or GSM standards, or that same system could be operated in the United States with a CDMA2000 radio personality profile. The one system could also be operated as a multimode radio in an environment where both wideband and narrowband CDMA communications are employed. Radio agility is important in situations where standards are fluid. Consider the evolution of the 3GPP standard and the length of time required for the standard to stabilize. It is also important during transitionary periods. For example, as we move from 2G to 3G mobile cellular systems multiple standards will need to coexist: Personal Digital Communication System (PCS) Global System for Mobile communications (GSM), IS-95, Personal Handyphone System (PHS), DECT, EDGE, GPRS, IMT-2000, CDMA2000 and so on. Multistandard support will be a fact of life for the foreseeable future.
When the 4G wireless network build-out takes place, multimode operation will be required to support third-generation wireless direct-sequence spread spectrum and OFDM systems. From a network operator perspective BTS configurability could be used to dynamically allocate radio resources. Soft radios can be viewed as a means to future-proof infrastructure investments by keeping radio hardware from becoming obsolete as new standards and techniques become available.
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