With network investments in a lull, infrastructure spot renovations are more common than teardowns and rebuilds. These spot upgrades are melding new technologies with legacy infrastructure and creating a need for linking leading-edge high-speed technologies with legacy protocols. This creates situations not yet defined or approved by an industry standards body. Fixed solutions are ill-equipped to handle these situations, as they have neither sufficient intelligent glue logic nor the field-upgradeability to incorporate a newly approved standard. For example, engineers are faced with the challenge of how to rapidly mesh ubiquitous Ethernet LANs with long-haul optical links and high-bandwidth network processors that use the System Physical Interface 4 Phase 2 (SPI-4.2).
Through the use of flexible bridging technologies, the existing optical infrastructure can support today's data-heavy traffic patterns. These bridge designs strive to use as much existing technology, protocols, interfaces, chips, and intellectual property as possible. And a field-programmable gate array (FPGA) intellectual-property core can add the final touches such as packet framing, jumbo packet support, flow control and remote system configuration. Ultimately, this technology leveraging extends the existing infrastructure life span and allows new features without overly taxing unavailable corporate investment.
One common example is the need to connect Ethernet to Sonet. As 10-Gigabit Ethernet is not yet commonplace, we will consider an interface between an OC-192 (10 Gbits/second) Sonet port and 10 ports of Gigabit Ethernet. On the Ethernet side would reside a Gigabit Ethernet transceiver and a Gigabit Ethernet media access controller (MAC). The MAC completes the physical- to link-layer conversion and presents the data through an SPI-4.2 interface. On the Sonet side is an optical transceiver and an optical framer. This also presents an SPI-4.2 interface, but there is significant bridging technology needed between these two SPI-4.2 interfaces.
An FPGA is best suited for housing this bridging technology. The level of wire-speed throughput required demands we use an FPGA or ASIC implementation, rather than a CPU or digital signal processor (DSP). The upgradeable feature requirement, as well as the ASIC's high upfront cost, determines our choice should be an FPGA.
Continuing with the desire to use off-the-shelf technologies wherever possible, we can look for a vendor with a standard design for the packet-over-Sonet Level 4 interface (POS-PHY 4), which is the basis for the SPI-4.2 standard. Interfacing the two POS-PHY cores can require custom FPGA intellectual-property core development for key areas such as packet framing, jumbo packets and flow control.
First, let's look at packet framing. Two major submodules need to be designed within the FPGA core. An Ethernet-to-Sonet multiplexer handles the multiplexing or interleaving of packets in the ingress direction. A Sonet-to-Ethernet demultiplexer handles the egress direction where packets are redistributed to the correct port.
During the multiplexing process, two important factors need to be considered. First, while combining multiple Ethernet ports into a single Sonet port, an additional routing header must be inserted. This header contains the destination port ID, and is used on the demux side to route the packet to the appropriate port.
Another challenge is managing running disparity, which requires that an even number of 1s and 0s be transmitted to avoid a dc offset that can lead to corrupted data on fiber. Both of these concerns are addressed with the use of the Generic Framing Procedure (GFP). This procedure establishes a standard method for adding an additional routing header, as well as the 8-bit to 10-bit (8B/10B) data conversion to manage running disparity.
Support for jumbo packets, while not required, is another feature to consider. Ethernet traffic has been using 1,500-byte frame sizes since about 1980. However, with increasing speeds and bandwidth there is an advantage in moving to larger sizes. For example, it has been calculated for Transmission Control Protocol (TCP) networks that larger segment sizes significantly increase throughput. A standard growing in popularity uses 9,000-byte frame sizes, chosen to handle 8-kbyte pages. Thus, new technologies being brought to market should consider jumbo packet support as a design requirement.
The key effect of this requirement is an increase in memory demands. In considering an FPGA implementation, 10 channels of Gigabit Ethernet traffic with 9-kbyte buffering can quickly overrun even the largest FPGA resources. But flexible memory architectures are available in newer FPGAs. By designing a memory arbiter that manages a shared FIFO structure and allocates blocks of paged memory dynamically, it is possible to avoid allocating dedicated memory for each port. With this arbitration scheme, the total memory requirement is cut in half.
A further feature enhancement to be considered is packet-over-Sonet flow control. Through the use of control packets embedded in the Sonet traffic, the end-of-line condition is known at all times. Individual channels can then be paused to avoid data overflows and dropped packets. Features such as flow control and jumbo packet support do introduce additional complexities and engineering, though they also represent potential for product and price differentiation.
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