Digital receivers, sometimes called digital downconverters or digital drop receivers, are the fundamental building block of the software radio industry. They revolutionized the communications industry soon after the first monolithic silicon devices were introduced at the beginning of the 1990s.
Digital receivers accept digitized samples of IF or RF signals typically derived from a radio antenna. They utilize digital signal-processing techniques to translate a desired signal at a certain frequency down to dc and then remove all other signals by low-pass filtering.
The three essential elements of a digital receiver are the local oscillator, the mixer and the filter-terms appropriately derived from their discrete analog circuitry counterparts in a traditional superhet radio. The local oscillator consists of a phase accumulator (an adder and a register) and a lookup table to generate digital quadrature sine and cosine signals. The accumulator is clocked at the A/D converter's sample clock frequency so that the local oscillator output sample rate matches the A/D sample rate. Frequency control is achieved by programming the phase increment for each clock.
The complex mixer consists of two digital multipliers that accept digital samples from the A/D and the local oscillator. They produce a complex representation of the input signal, which has been translated down by the frequency setting of the local oscillator. By appropriately tuning the local oscillator, any frequency band of interest can be centered on 0 Hz.
The complex FIR low-pass filter accepts I and Q samples from the mixer. By judicious choices for coefficient values and the number of taps, it can implement a wide range of transfer functions, each with specific passband flatness, shape factors and stop-band attenuation to reject unwanted signals outside the band of interest.
At the filter output, a decimation stage drops all but one of every N samples, consistent with the bandwidth reduction of the filter. This produces a complex baseband output suitable for subsequent signal-processing tasks such as demodulation, decoding or storage. By suitable reordering and sign changing of the I and Q output components, a real representation of the signal is also available. A useful definition of the decimation factor is the ratio between the input sampling rate and output bandwidth.
Digital receivers are divided into two classes appropriately named for the relative range of output signal bandwidths: wideband and narrowband. Digital receivers with minimum decimation ranges of 32 or more generally fall into the narrowband category and are extremely appropriate for extracting voice signals with bandwidths of several kilohertz from digitized input signals with bandwidths of several tens of megahertz. In these applications decimation factors can be 10,000 or higher.
Because the complexity of the FIR low-pass filter is proportional to the decimation factor (and inversely proportional to the bandwidth), ASIC implementations of narrowband receivers usually rely on an initial CIC filter stage to perform high decimation factors without requiring hardware multipliers. Since the CIC filter produces a sloping frequency response in its passband, its output is delivered to a CFIR (compensating FIR filter), which restores an overall flat passband response. Finally, a PFIR (programmable FIR) filter is used to achieve the desired final frequency response.
Market demand for narrowband applications such as wireless basestations has inspired ASIC receiver chip offerings. However, with the migration to new wideband-CDMA wireless modulation schemes, narrowband receivers are falling short of the mark. Required bandwidths of 5, 10 and even 20 MHz are now mandated by technologies entering mainstream applications. But because of the CIC front end, most ASIC narrowband receivers impose a minimum overall decimation of 32. With a 100-MHz input-sampling rate, this yields a usable output bandwidth of only 2.5 MHz.
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