With the advent of new high-bandwidth wireless data technologies such as 802.11b (Wi-Fi, WLAN), design efforts based on legacy chipset architectures have become a formidable problem. Providing the required processing power while ensuring maximum flexibility remains the key design challenges.
The 802.11b solution requires high processing power due to high data rates and complexity. Flexibility facilitates faster adaptation of new standards, decreasing the risk of becoming obsolete. There are traditionally two ways of implementing this emerging wireless technology, the ASIC route and the DSP route. However, both types of implementations have their own advantages and disadvantages.
A typical implementation of 802.11b running at 11 Mbit/second on a 32-bit DSP typically requires 4 billion operations per second (GOPS) for a pure DSP-based solution. There are very few DSPs available today that have that required processing power. A pure ASIC-based 802.11b solution typically requires 200K gates, which is less than the ASIC gates that are required for a DSP with a high processing power of 4 GOPS. The downside is that the pure ASIC-based solution, compared to a DSP, requires a longer design cycle, higher initial costs and is not flexible.
After analyzing the advantages and disadvantages of both the pure DSP-based and pure ASIC-based solutions, our design team decided to take the best of both architectures and developed a hybrid solution onto a configurable core. With this approach, the DSP and hardware accelerators were designed to share tasks and achieved the processing requirements of an 802.11b implementation by offering the flexibility and the processing power.
Implementation of 802.11b can be done using a DSP-based configurable processor. The four modules implemented on hardware accelerators include the decision feedback equalization (DFE), channel matched filtering (CMF), carrier error compensation (CEC) and fast Walsh transform (FWT). Also included here are the analog front end (AFE), the RF and host interfaces.
Source: Hellosoft Inc.
Functions were implemented as hardware accelerators. For example, the performance of the target DSP was initially analyzed for the pure DSP-based implementation of 802.11b solution. The target DSP is a dual-core synthesizable 32-bit DSP from ARC International, consisting of a DSP and a RISC core. The dual-core can run at 200MHz and has a processing power of 200 million operations per second (MOPS), which is very low for 802.11b implementation. With the help of hardware accelerators, one can implement 802.11b on a dual-core that provides both flexibility and low gate count. The medium access control (MAC) functions of the 802.11 standard can also be implemented on the RISC core of the processor, thus providing a tight coupling between the physical and MAC layers that is required in 802.11b technology.
In the implementation of 802.11b on the DSP-based configurable processor, the majority of the computation is required for decision feedback equalization (DFE), channel matched filtering (CMF), carrier error compensation (CEC) and fast Walsh transform (FWT). With these four modules implemented on hardware accelerators, the DSP can easily support the rest of the DSP functions.
In the design, four hardware accelerators add to 160K FPGA gates. The hardware accelerators are developed in Verilog and can be integrated with the soft dual-core on any FPGA. The entire solution including the dual-core and the hardware accelerators requires less than 150K ASIC gates.
From our results, it was clear that hybrid solution offered the best of pure ASIC- and DSP-based solutions. The hybrid approach overcomes the disadvantages of pure ASIC-based and pure DSP-based solutions by providing flexibility, low initial cost, low design cycle and required processing power for an 802.11b solution.