Advancing GSM architectures many not seem like a sexy topic in an age where 2.5G and 3G technologies are the talk of the town. However, the reality is that like AMPS in the past GSM is becoming a base technology that all future mobile devices must support to be successful.
To serve as a base technology, GSM must move from a high-price wireless option to a low-cost radio architecture that can be embedded in a host of mobile designs. One way to cut price is by bringing higher levels of integration in the transmit path of a GSM design. And in the transmit path, cost savings can be seen through the integration of power control and power amplification functionality in the same chip architecture. The article that follows will show you how.
Accurate Control Needed
The GSM standard, as well as other digital wireless communications standards, requires accurate control of a mobile unit's transmitted power over a wide dynamic range. Accurate power control is required to meet system specifications under operating conditions like temperature and supply voltage variation.
Today, voltage-controlled power amplifiers (VCPAs) are not able to meet these requirements without an additional power-control circuit. The most common solution today is a power-control loop based on a directional coupler with a peak detector and a comparator, which requires 20 to 50 mm2 of board space and costs around $0.50.
The design of the control loop depends very much on the characteristics of the power amplifier and can require weeks if not months of optimization. In addition, the directional coupler at the output is adding significant losses to the generated power, thereby resulting in higher power dissipation and reduced talk time.
The answer to this problem lies in an integrated that merges power amplifier and power-control circuitry. Below we'll compare some power-control for VCPAs versus an integrated solution. During the discussion, we'll look at:
- digital control
- supply voltage control
- supply current control
- closed loop output power (voltage) control
1. Digital Control
The digital control technique is performed by a microprocessor. Under this approach, the microprocessor selects the right VCONTROL value from a look-up table (based on actual information about external factors like supply voltage, temperature, frequency, etc.) to transmit the required power level.
The big advantage of the digital control principle is that no additional active and passive components are required within the transmit power path. However, there are many more disadvantages. First, control is based on steering, there is no feedback to correct for changes in external parameters during a transmit burst. Second, it takes some resources of the microprocessor. Finally, extensive calibration of each phone is required in the production process to correct for component variation. Based on these disadvantages, digital control is not used in most handheld applications.
Supply Voltage Control
With supply voltage control, the collector or drain voltage of the last one or two amplifier stages are controlled (Figure 1). This limits the voltage swing of the RF power transistors, hence reducing the RF output power, as long as the amplifier is driven into saturation.
Figure 1: Diagram of a supply voltage control architecture.
The output power in the supply voltage control example shown in Figure 1 is related to the quadratic of the supply voltage. The fact that there is a simple quadratic relation between control signal and RF output power provides four advantages:
- Output power is predictable after a simple calibration
- The burst template (power versus time) can be easily shaped
- Control of PA is possible over a wide dynamic range
- No additional losses in the output circuit, compared to circuits with a directional coupler
But while the supply-control approach offers some significant benefits, it also has some big drawbacks. A MOSFET is required to switch the large supply current, adding size and cost in the mobile. The MOSFET also has a 20- to 100-milliohm on resistance, which reduces overall system efficiency.
Designers will sometimes use the supply-voltage control architecture in designs that already need an external MOSFET switch in the supply line. However, in designs not offering an additional MOSFET, the use of the supply-voltage control approach will probably be avoided.
3. Supply Current Control
Supply current control is based on a quadratic relation between the output power of the PA and the supply current (Figure 2).
Figure 2: Diagram of the supply current control method
The supply current of the power amplifier is converted into a voltage over RSENSE in the supply line, and compared with a voltage across R1, which is proportional with the control voltage VPC (V(R1)= VPC.R1/R2). The error amplifier controls the gain of the power amplifier in such a way that V(RSENSE) and V(R1) are always equal, so accurately setting the PA current at:
If the output power versus supply current characteristic is known for a given PA, the output power can accurately set. The advantage of this configuration is the possibility to integrate the power control circuit on the same chip with the PA, with only the sense resistor external. But there are the following disadvantages to this method:
- Power loss at higher power levels due to voltage drop across RSENSE
- Limited dynamic range due to low sensitivity at low power levels. The voltage across RSENSE becomes small compared to noise and offset voltages of the error amplifier
- RSENSE should be temperature stable and able to handle the high current, which requires a relatively large surface-mount component
- The error amplifier must have a rail to rail input common mode voltage range
4. Closed-Loop Output Power Control
Another principle of power controlling is the closed loop approach. Under this approach, which is shown in Figure 3, the RF output power is sensed via a directional coupler and is detected across a fast Schottky diode. The resulting voltage signal is directly proportional to the RF peak voltage and is compared with a reference voltage in an error amplifier. The loop controls the power amplifier gain via a control line to force the detected voltage and the reference voltage to be equal. Power control is accomplished by setting the reference voltage.
Figure 3: Diagram of a closed-loop output power control with a differential node.
The advantage of the closed-loop power control method is an excellent behavior under mismatched conditions. This method performs well under mismatch because the directional coupler can distinguish between incident and reflected power.
There are also some disadvantages. First, output power is lost due to insertion loss of the directional coupler. This leads to system efficiency degradation, comparable to the losses in RSENSE in the current control. Second, external components such as coupler and diode detector are expensive and consume additional PCB area, (i.e. the component count is increased). Third, diode detector in combination with high-ohmic input impedance of error amplifier diversely affects frequency characteristic of power control loop. Finally, error amplifier should have rail-to-rail input common mode voltage range.
Now that we've discussed the four options, let's examine a real-life implementation of the closed-loop power control architecture. Figure 4 shows a good example of a closed-loop architecture. The CMOS device shown in this figure consists of an amplifier for the detected RF voltage from the sensor, an integrator, and an active filter (at DAC input). This allows the build up a PA control loop for cellular systems with a small amount of external components.5 The detector range lies between -20 to +15 dBm. If a directional coupler is used, this detector range complies to the RF output power range of GSM, DCS and PCS systems
Click here for Figure 4
Figure 4: Diagram of a power controller housing a closed-loop output power control architecture.
In the architecture shown in Figure 4, the Schottky diode for power detection (sensor) is biased by an integrated current source of 30 μA. Variations of the forward voltage with temperature have no influence on the measured signal, because they are canceled by the sampling around the switched capacitor amplifier (OP1).
An external DAC with 10-bit resolution is employed to control the loop. The integrated active filter, on the other hand, smoothes the voltage steps of the DAC and avoids a feedthrough of the DAC output voltage step transients into the switching spectra of the RF output signal.
In this circuit, the DAC and the sensor signal are added and buffered by amplifier OP1. The error signal is integrated by the operational amplifier OP4, which delivers the PA control voltage across the external capacitance CINT, between VINT(N) and VC. The shape of the rising and falling power burst edges is determined by means of the DAC voltage.
The power controller shown above has been designed to operate in burst mode, as required in TDMA system. The initialization of switches S1, S2, S3, S4 and S5 depends on the required timing and DAC signal.
This circuit offers excellent control of output power. But it also provides some challenges in a system design. First, there are losses due to the need for an external coupler. Next, the switching capacitance technique required to reject DC offset requires the integration of an external diode. Finally, to initialize this circuit, designers must implement digital logic, which increases the die area of the power controller slightly.
Based on these problems, designers can see that the real win is an integrated power detector with DC offset compensation onboard. Let's look at this architecture further.
The Integrated Approach
The concept of the integrated power detector discussed below is based on an RF PA that operates in class AB. In this mode the DC current IC1, flowing through the collector of output transistor T1, is proportional to the output power and this effect can be used to monitor the amount of power delivered to the load.6
Figure 5: Diagram of the an integrated power detector based on a current mirror technique.
The implementation of this idea is shown in Figure 5. In the architecture highlighted in Figure 5, the output transistor (T1) and mirror transistor (T2) are dimensioned in a way that the signal current IC2, which flows through the mirror transistor T2, is a replica of the current flowing through the output transistor T1 - IC1:
A1 is area of output transistor T1
A2 is the area of mirror transistor T2
The DC current, IC1, is a gauge of the RF output power and accordingly IC2 would be a scaled representative of it. The detected signal in this case is the current IC2, which could be transferred into a voltage using the resistor R, connected between collector of T2 and supply voltage Vdd1.
The capacitance C rejects undesired RF at the detector output. The dynamic range of ΔVDET=IC2R is adjustable by means of the resistor value R and the area ratio between T1 and T2.
When the power is low, the biasing circuit of T1 determines IC1 and accordingly IC2. When powered on, IC1 is quite stable at different temperatures. Hence, IC2 is quite stable as well (Figure 6). The measurements shown in Figure 6 were done using a modified version of a power amplifier7 with an integrated detection circuit described below.
Click here for Figure 6
Figure 6: Detected mirror voltage output at different temperatures.
A important advantage of the mirror transistor concept in comparison to the coupler and the diode detector configurations is the low degradation of power added efficiency (PAE). For a coupler, the system efficiency will be decreased by about 5 percent. In the mirror transistor configuration, PAE losses depend on the mirror ratio and can be estimated by:
PAE1 is the power added efficiency of power amplifier without mirror transistor
PAE2 is the power added efficiency of power amplifier with mirror transistor
If an area ratio between T1 and T2 of 200 to 1 is chosen, the power added efficiency loss is .
A comparison between the current mirror detector and the diode detector is shown in Table 1.
Table 1: Comparison of Current-mode and Diode Detectors
||Diode detector + coupler
||Mirror transistor detector
||Diode, directional coupler, matching & decoupling components
||Mirror transistor is integrated at the output stage of the power amplifier
||Degradation due to coupler losses
||Very low losses (approx. 0.5 %)
||Frequency response of coupler and detector influence the entire loop characteristic
||Negligible influence on the bandwidth of the power control loop
||Fixed dynamic range, adjustable by R changes in parallel to the detector diode, has to be done during design phase
||Adjustable dynamic range by means of mirror ratio
||Sufficient thermal stability
||Good thermal stability due to compensated biasing
||No detection of radiated power
||Low additional cost
Integrated Power-Control Loop
Based on the current-mirror detector and the closed loop with summation node concept, a new circuit for RF power control application was implemented in a power amplifier MMIC. A schematic of the MMIC is shown in Figure 7.
Click here for Figure 7
Figure 7: Schematic of a PA MMIC integrating current-mirror and closed-loop power control technologies,
In Figure 7, the 10-bit DAC signal VDAC, is filtered by an RC lowpass filter and converted into a current via R1:
This current is added to the detected current delivered from the current mirror (IDET) and its difference is buffered by Op1:
The error signal is amplified by Op2 :
Substituting Equation 6 in Equation 7, we have:
This control voltage changes the output power POUT(IDET) according to the equation:
where T is a closed loop transfer function and equals:
and G is an open loop transfer function and can be expressed as:
As designers can see, closed-loop accuracy strongly depends on the open loop transfer characteristic (G), which is a function of power control loop gain (R2R4/R3) and transfer characteristic of PA [ADET(T0,VSUP)], which could have some temperature and supply voltage variations. Accurate trade off between power control loop gain and some pre-compensation of the control curves allows minimization of deviations in the closed loop gain T. If infinite gain of the power control loop is assumed, closed loop gain is 1 and IDET is approximately equal to IDAC. Thus, the power setting depends only on the accuracy of the detector.
Gain vs. Phase Margin Tradeoff
In the integrated architecture shown above, designers must make a tradeoff between high gain and sufficient phase margin. In traditional discrete power-control solutions, there are three poles from the power amplifier and detector in combination with the high ohmic input impedance of the error amplifier and the dominant pole, which sets phase margin. Phase margin strongly depends on the distance between dominant pole and the pole closest to it. Shifting of the dominant pole to the lower frequency is limited by the slew rate, which is responsible for a proper ramp up and ramp down.
In the integrated solution there are two poles, which makes splitting between poles much more flexible. In our case we have the following settings for the most critical power levels of 23 dBm (the highest slope):
3dB frequency of the integrator (dominant pole)
fC2=1 MHz 3dB frequency of PA (for power level POUT = 23 dBm)
G0 = 36 dB low frequency open loop gain
Qm = 36 deg. phase margin (for power level POUT = 23 dBm)
This choice allows us to perform ramping up and ramping down without any overshooting or deteriorating low limit of GSM mask.
A power amplifier with a fully integrated detector and power control has been designed for GSM systems with constant envelope modulation schemes. It utilizes the behavior of class AB power amplifiers in addition to a simple power-control circuit, which does not require an expensive technique to eliminate detector offset and thermal issues. The proposed solution will significantly reduce the PCB space, component count, and cost of the PA controlling system.
- Frost & Sullivan, www.frost.com
- 3GPP TS 45.005 V4.3.0 (2001-04); 3rd Generation Partnership Project; Technical Specification Group GSM/EDGE Radio Access Network; Digital cellular telecommunications system (Phase 2+); Radio transmission and reception
- AN1599 "Power Control with the MRFIC0913 GaAs Integrated Power Amplifier and MC33169 Support IC", Motorola, Inc.1997.
- Specification "MAX 4473, Low -- Cost, Low -- Voltage, PA Power Control Amplifier for GSM Applications in 8 -- Pin μMAX", Maxim.
- Specification "PCF5078 Power Amplifier Controller for GSM and PCN systems.", Philips product specification, 1999 Jul 29.
- D.P Prikhodko, J. Cairo, H. Visser , WO 01/18958 A1 "An amplifier for use in a mobile phone." 15.03.2001.
- Data sheet "BGY241 UHF amplifier module", 1998 Aug 17
- UBA1711 Controller for GSM/DCS/PCS GaAs FET power amplifier", Objective specification, Phillips Semiconductors, 15 Apr 2002
- ETSI, Draft GSM 11.10-1 V9.0.1 (2000-07) Digital cellular telecommunications system (Phase 2+); Mobile Station (MS) conformance specification", Release 2000, Conformance Specification
- Philips Semiconductors, PCF 5079 Dual Band Power Amplifier Controller for GSM, PCS and DCS", Objective specification, Feb 07, 2001
- European Microwave Conference in Milan 2002: P. Lok, F. van Straten, D. Prikhodko, R. Burdenski, U. Maurer, J. Cairo, "Power amplifier with integrated power control loop.", EuMC Proceeding (2).
About the Authors
Pieter Lok is innovation manager at Philips Semiconductors. In this role, Pieter is involved in the long-term business and technology development strategy for within Philips' RF Modules business unit. Pieter graduated from Technical University of Delft, where he earned a master's degree in electrical engineering in 1980. He can be reached at firstname.lastname@example.org.
Freek van Straten is an advanced development manager at Philips Semiconductors. In this role, Freek is responsible for RF product concept development. Freek holds degrees in physics and electronics and can be reached at email@example.com.
Rudolf van der Last is an RF module technology manager for mobile applications at Philips Semiconductors. He graduated from the Technical University of Eindhoven, The Netherlands, receiving a bachelor's degree in electrical engineering. Rudolf can be reached at firstname.lastname@example.org.
Dima Prikhodko is an RF development engineer at Philips Semiconductors. He received degrees in the physics of semiconductor devices and electrical engineering from the Moscow Institute of Electronic Engineering (Technical University) in 1997. Dima can be reached at email@example.com.
Ralf Burdenski is a principal system architect at Philips Semiconductors. He received a degree in electronic circuit design and a Ph.D. in high-speed sampling devices from Technical University of Ilmenau, Germany. Ralf can be reached at firstname.lastname@example.org.
Ulrich Maurer is a development engineer at Philips Semiconductors. He graduated with a degree in telecommunication technology at the Technical Department of the Georg-Simon-Ohm-Academy in Nuremberg, Germany. Ulrich can be reached at email@example.com.