System architects spend considerable effort and time designing high-performance clock and sinusoidal oscillator circuits for telecommunications basestations. A single-chip transceiver incorporates many of these signal generators but still requires a reference clock. Since basestations within a single network typically synchronize to each other, this reference clock must be time-aligned to a network-wide timing signal.
This article discusses how a high-performance clock generator working in conjunction with one or more integrated transceivers simplifies the overall design and reduces complexity and cost while resulting in excellent system receive and transmit performance. Even if the basestation loses the timing reference signal for an extended period, all basestations remain synchronized within the network.
Basestation Clock Architecture
One of the most often cited parameters of a basestation is its carrier (or local oscillator) frequency. The synthesizer that generates the local oscillator is an important part of the basestation, but as all system designers know, the local oscillator is only one of several internal frequencies that basestations need. In the transceiver alone, in addition to the local oscillator (LO) supplying the carrier frequency to the mixer stages, the data converters need sampling clocks, the digital filters need clocks, and the I/O bus usually requires a data clock.
A system architect can save significant design time and cost by using an integrated transceiver, as shown within the dashed box in Figure 1. Along with receiver and transmitter circuitry, single-chip transceivers incorporate phase locked loops (PLLs) that generate the clock and sinusoidal signals needed by the various signal processing blocks. Even highly integrated transceivers, however, require a reference clock input.
Figure 1: 2×2 MIMO Basestation Transceiver Architecture
(Click on image to enlarge)
Single-chip 2×2 multiple input multiple output (MIMO) transceivers such as the Analog Devices AD9356 and AD9357 provide two different options for the reference clock. An external crystal used with the on-chip digitally controlled trimming circuit (DCXO) is one option while providing an external clock to the device is the other. The AD9356/7 accepts reference clock frequencies ranging from 32 MHz to 48 MHz.
Subscriber stations such as customer premises equipment (CPE) devices use information transmitted by the basestation to synchronize to the wireless network. A CPE device fine-tunes its local oscillator frequency while also time-synchronizing to the basestation master clock. For this reason, the external crystal plus DXCO option mentioned above is a low cost and high performance solution for this application.
Basestations have additional requirements. For example, operators usually require the frame and symbol boundaries for all stations within a particular network to be time-aligned. Since basestations provide the timing information to their associated subscriber stations, this implies that all basestations within the network must lock to an external timing reference.
System architects commonly employ one of two methods to synchronize basestations. One method uses the one pulse-per-second (pps) output from a GPS receiver (Reference 1) while the other uses the network timing protocol found in the IEEE 1588 specification (Reference 2). In both cases, the reference clock input to the transceiver shown in Figure 1 synchronizes to the timing reference (e.g. the 1 pps GPS clock).
Basestation Reference Clock Design Considerations
As shown in Figure 1, integrated transceivers use the reference clock as an input to PLLs. In the case of the RFPLL, the basestation multiplies the reference clock up to the LO frequency. This multiplication can be a factor of eighty or more. For this reason, the phase noise of the reference clock must be very low for the transceiver to achieve high performance.
The reference clock must also synchronize to an external timing reference, which in the case of GPS is 1 pps.
An important corollary to synchronization is the concept of holdover. If the timing reference is lost (for example if a building blocks the GPS satellite signal for some period of time each day), the reference clock must not deviate from where the timing reference would have been had it been present. Specifications such as ANSI/T1.101-1987 (Reference 3) divide the holdover requirements into various levels (strata), each of which specifies a different maximum deviation allowed over a particular period. Stratum 3E, an additional level defined in Bellcore GR-1244-CORE, requires that a clock source deviate no more than 10 parts-per-billion over 24 hours.
As discussed in the N×N MIMO Systems section below, if a basestation uses two or more transceivers in a multiple-in-multiple-out architecture, the basestation must synchronize all transceivers to the same timing reference. For low parts count and cost, the reference clock should be capable of providing several identical outputs, each of which can drive different transceiver blocks.
Case Study: Providing an External Clock
The following case study uses the AD9356/7 2×2 MIMO integrated transceiver as part of the basestation system. As mentioned above, the AD9356/7 requires a reference clock frequency between 32 MHz and 48 MHz. Synchronizing this clock to the timing reference requires a flexible PLL with excellent phase noise performance and the Analog Devices AD9548 Quad/Octal Input Network Clock Generator/Synchronizer was chosen is ideally suited to this task. The timing reference output connects to one of the AD9548 reference inputs and a low-phase-noise clock connects to the system clock input. The output is programmed to be the 32 MHz to 48 MHz reference clock required by the AD9356/7. Figure 2 shows a block diagram of a GPS-synchronized system.
Figure 2: Basestation Architecture with GPS Reference
(Click on image to enlarge)
Some network clock generators can tolerate an extremely wide range of input frequencies, allowing for a variety of timing references and low phase noise clocks. Choosing the input frequencies wisely can simplify the design, reduce cost, allow for best transmit/receive performance, and meet the required holdover specifications.
The AD9548 locks the output clock to the timing reference using a digital phase-locked-loop (DPLL) rather than an analog PLL. This technique results in a system with excellent holdover performance, limited only by the timing drift of the system clock source. Further, the phase noise of the system clock, not the timing reference, governs the phase noise performance of the AD9548 output clocks so the device tolerates noisy timing references and does not pass this noise to its outputs.
Maximizing Reference Clock Performance
The wide range of input and output frequencies that can be used with network clock generators present the system architect with many options for optimizing the performance of the output clock.
For example, highly stable clock sources of 25 MHz and lower are more plentiful and are generally less expensive than higher frequency clock sources. If the system clock (sysclk) input shown in Figure 2 is less than 50 MHz, the frequency doubler in the AD9548 may be used to double the system clock with minimum added phase noise. From this higher frequency, the system clock PLL then multiplies the clock to approximately 1 GHz.
The designer must also choose the DPLL output frequency and the resulting post divider ratio. Faster slew rates that result from higher DPLL output frequencies generally help reduce phase noise but also can result in spurs folding back into the spectrum. For the AD9356/7 reference clock, an effective compromise sets the DPLL output frequency to 240 MHz and the post divider to a value of 6, resulting in a final output frequency of 40 MHz. Figure 3 shows the resulting phase noise of the AD9548 when using these settings.
Figure 3: Analog Devices AD9548 Phase Noise vs. Frequency
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Figure 4 shows the resulting integrated phase noise of the output of the AD9356 when transmitting at 2500 MHz, using the AD9548 to supply the reference clock. The AD9548 evaluation board can use its own on-board system clock XO (the stock configuration) or an external clock. The plots in Figures 3 and 4 show the AD9548 configured to use a 12.8 MHz oven-controlled crystal oscillator (OCXO) input to its system clock. The AD9548 was not synchronized to a timing reference for this test.
Figure 4: Analog Devices AD9356 Integrated Phase Noise, 2500 MHz Carrier
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Using this configuration, the transmit EVM at the output of the AD9354 using a WiMAX 802.16e 64-QAM waveform is typically better than –38dB.
As mentioned above, the system clock source to the network clock generator must have low phase noise to ensure that the resulting EVM of the transceiver is as low as possible. In addition, the system clock source must possess very good short-term stability, especially if the 1 pps signal is the network timing reference. To synchronize to the GPS timing reference, the network clock generator must use a very narrow PLL bandwidth. Such a narrow bandwidth means that the system clock source must have very low jitter in order for the network clock generator PLL to remain locked. A high performance source such as an OCXO meets these requirements and is normally present in basestations.
N×N MIMO Systems
N×N MIMO systems require multiple transceivers and which each require identical versions of the external reference clock. Network clock generators that can provide multiple identical outputs which can be separately routed to each transceiver eliminate the need for clock buffer and clock distribution devices. The AD9548 can provide up to four differential LVDS/LVPECL or eight single-ended CMOS outputs. The solid boxes and signals in Figure 5 show a 4×4 MIMO system with common, phase-locked reference clocks and the dashed lines and boxes show the system expanded to a 6×6 MIMO architecture.
Data samples transfer between the AD9356/7 and the BBP on a JESD-207 compliant parallel port interface and the AD9356/7 generates the parallel port data clock. In 4×4 and higher-order systems, the BBP can force the data clocks of all of the AD9356/7 transceivers to synchronize by sending pulses to each of the transceivers at the same time. This ensures that the data samples from and to each transceiver are time-aligned.
Figure 5: N×N MIMO Basestation Architecture with GPS Timing Reference
(Click on image to enlarge)
A high performance clock generator, synchronized to an external timing reference and working in conjunction with one or more integrated transceivers simplifies the overall design and reduces complexity and cost of a telecommunications basestation. The design easily extends to N×N MIMO basestation architectures. These devices integrate most of the clock and sinusoidal generators while still achieving excellent system receive and transmit performance. Basestations within a network remain synchronized to each other even if the timing reference signal is temporarily lost.
About the Author
- IEEE 802.16-2004 IEEE Standard for Local and Metropolitan Area Networks, October 1, 2004
- IEEE 1588-2008 IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems; July 24, 2008
- ANSI/T1.101-1987 Synchronization Interface Standards for Digital Networks
is a senior applications engineer, RF Group, Analog Devices, Inc.
He focuses on integrated WiMAX transceivers at Analog Devices. He holds a B.S. in Electronic Engineering from California State Polytechnic State University in San Luis Obispo, CA. firstname.lastname@example.org