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Protecting FPGAs from power analysis

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re: Protecting FPGAs from power analysis
DrFPGA   7/19/2010 4:21:02 PM
New FPGA design tools have some automatic power reduction algorithms (like clock gating). At first glance, it would seem that these tools would actually make it easier to attack such a design using power analysis. Maybe there is a way to use them to more easily obfuscate power use however if clock gating can be turned on and off in a controlled (but random) fashion.

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