Breaking News
Design How-To

Time is right for clockless design

6/10/2010 01:00 PM EDT
11 comments
NO RATINGS
Page 1 / 2 Next >
More Related Links
View Comments: Newest First | Oldest First | Threaded View
Page 1 / 2   >   >>
NatM
User Rank
Rookie
re: Time is right for clockless design
NatM   9/13/2010 6:30:10 PM
NO RATINGS
Octasic has introduced a family of DSPs that are based on asynchronous technology. This white paper shows how asynchronous technology offers a 3x gain in performance per watt. You can read the white paper here: http://www.octasic.com/en/tech/opus_dsp.php

Antoine Sirianni
User Rank
Rookie
re: Time is right for clockless design
Antoine Sirianni   7/24/2010 8:46:56 AM
NO RATINGS
Should you think you can afford it.

p_g
User Rank
Rookie
re: Time is right for clockless design
p_g   7/23/2010 5:55:46 AM
NO RATINGS
Antoine, I wish to bin lot of them in high speed bin :) And this is what async design can achieve.

Antoine Sirianni
User Rank
Rookie
re: Time is right for clockless design
Antoine Sirianni   7/20/2010 8:40:03 PM
NO RATINGS
I hope you are not going to bin too many of them ;-)

p_g
User Rank
Rookie
re: Time is right for clockless design
p_g   7/16/2010 10:32:42 AM
NO RATINGS
Clockless design certainly have a big advantage of low power and mobile computing devices running on battery can gain a lot here. Since the speed of async design is purely based on process corner of silicon, it helps a lot in binning where fast part can serve great speed.

DKC
User Rank
Rookie
re: Time is right for clockless design
DKC   6/21/2010 9:35:12 AM
NO RATINGS
"Clockless needs standard languages" I worked on the SystemVerilog committee and attempted to add support for asynchronous constructs way back before it went to the IEEE - with no success. That failure encouraged me to investigate ESL solutions that would support asynchronous design using C++. So ~ 6 years on I have an extended C++ that will support asynchronous design - http://parallel.cc Good luck with SystemVerilog for asynchronous design - it's not much good for power aware design either.

Les Slater
User Rank
Rookie
re: Time is right for clockless design
Les Slater   6/15/2010 8:36:45 PM
NO RATINGS
Back in â??95 or so I had a lengthy discussion with Fred Pollack of Intel about microprocessor architecture. He was pushing long pipelines and fast clocks at the time. The penalties of pipeline flushes were discussed. I suggested that maybe a better use of Mooreâ??s Law might be to put multiple processors on a single die. His response was that the software industry was nowhere near prepared to effectively use such. That was only 15 years ago. When we got boxed into a technology corner we got serious. We are yet still at a primitive stage of parallel processing and asynchronous design may be more complex in SOME respects but I think the vision of the promise will bring positive results. And as for building a â??a complete system including sophisticated software...â?ť. Thatâ??s what the last paragraph of my previous post was alluding to.

Antoine Sirianni
User Rank
Rookie
re: Time is right for clockless design
Antoine Sirianni   6/15/2010 7:07:36 PM
NO RATINGS
There has been a long track of academic research on asynchronous design since 3/4 decades. Some companies like Handshake Solutions (not mentionned in the paper) have delivered mature solutions to the market. Yet there are less obvious drawbacks than tooling like: the lack of controllabilty (no time preemption, reduced test capability, problems with reset), the cost (extra area, extra nre). And you still need to build a complete system including sophisticated software... So up to you ...

Les Slater
User Rank
Rookie
re: Time is right for clockless design
Les Slater   6/15/2010 4:27:09 PM
NO RATINGS
"...the envelope is somehow constant for a given technology node." In the context of moving to clockless or mixed it seems that the concept of envelope is vague at best. There are obvious trade-offs though. The obvious one is lack of mature tools and experience. I believe that it will take a totally new look at methodology starting with the definition of the problem space. What do we really need to accomplish?

Antoine Sirianni
User Rank
Rookie
re: Time is right for clockless design
Antoine Sirianni   6/15/2010 12:35:41 PM
NO RATINGS
Design in the realm of silicon based systems is a matter of trade-offs and the envelope is somehow constant for a given technology node. If you put emphasis one hand, you will loose on some other. What is it that you loose designing asynchronous circuits? Besides, as far as I know, Dr. Strangelove in Stanley Kubrick's movie was inspired from John Von Neumann.

Page 1 / 2   >   >>
Top Comments of the Week
August Cartoon Caption Winner!
August Cartoon Caption Winner!
"All the King's horses and all the KIng's men gave up on Humpty, so they handed the problem off to Engineering."
5 comments
Like Us on Facebook

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Times on Twitter
EE Times Twitter Feed
Radio
LATEST ARCHIVED BROADCAST
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.
Flash Poll