In the last few decades the semiconductor industry has successfully and dramatically improved the capabilities of electronics, particularly in the areas of speed and power consumption. Each new technology node has brought the potential for even faster speed at even lower power levels.
While Moore’s Law has always been theoretically faithful in terms of its continued march forward with transistor density, the complexity of designing to advanced geometries flirting with atomic sizes has resulted in a frustrating paradox: it is not easy to take full advantage of the new nodes because high variations require design margins that limit the intrinsic technology potential.
Today, design engineers must evaluate tradeoffs between power and speed, typically compromising on one or the other. Yet, in an uncompromising consumer market that demands both higher performance AND longer battery life, what to “leave on the table” is a difficult and painstaking decision.
Designers have long sought the Holy Grail of a solution to maximize the performance vs. power trade-off. Fast designs that meet stringent power requirements. The ying and yang of complex IC design.
One such approach that has been looked at for many years as having great promise is asynchronous or clockless design technology. This technique has always seemed to be academically and conceptually a very viable method, but various attempts at making it a commercial success have never gotten traction.
For sure, self timed circuits which do not require any clock signal offer a wide range of benefits:
- Consuming power only where and when needed
- Reduced latency (never waiting for a clock edge)
- Robust to PVT variations (reduced design margins)
- Removal of system level blocks (clock trees, high freq PLLs)
- Operating at very low voltage
And, in fact, these improvements have been validated by multiple projects (industry and academic). So what has held companies back from adopting this approach and delivering chips that leverage its potential?
Despite a sincere enthusiasm, there is often a perception that asynchronous design does not work. This perception comes from a confusion between the validity of the technology and the ability to integrate asynchronous design inside an existing design flow.
Despite this perception, several companies today have been delivering chips based on an asynchronous implementation, showing breakthrough performances in terms of speed/power ratio (e.g. Achronix, Fulcrum, Octasic).
So when you hear “it does not work”, does it really mean “I don’t think I can use it myself”? Admittedly, the gains achieved through the use of asynchronous technology have to date required an extra degree of effort. These early successes have managed to deal with the challenges that have prevented asynchronous from being more broadly adopted, namely:
- How to combine asynchronous and synchronous circuitry on a single chip
- How to use an existing EDA flow, from simulation, through synthesis and timing
- How to guarantee performance
- How to support a timing driven flow with asynchronous technology
- How to test chips, maintain quality assurance
- How to validate on FPGA emulators