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Reducing switching power with intelligent clock gating

6/15/2010 06:00 AM EDT
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ahshabazz
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re: Reducing switching power with intelligent clock gating
ahshabazz   8/17/2010 8:33:34 AM
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Clocking a discrete logic gate. GALS clocking domains. This is why the study of fractals has become important to those in antenna design, 3D heat sink design, and distributive clocking.

DrFPGA
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re: Reducing switching power with intelligent clock gating
DrFPGA   7/28/2010 4:48:00 PM
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I can't tell from the article (or maybe I'm too literal) but is there actually a gate on the clock signal or is the clock enable on the register being used. In my digital design class we were told to never ever gate the clock signal. Setup/hold/skew would kill you. I know we need to do it some times, but I'm much more comfortable with an enable signal- and they are on all FPGA registers anyway. Anyone know for sure how this is implemented in hardware?

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