As microprocessor designs have grown considerably in complexity,
the use of hand-written directed tests in verification has dwindled.
Automated random test generators that cover the stimulus space more
efficiently have emerged in their place. These random test generators
create microcode test sequences, emphasizing the distribution of stimuli
across all meaningful values for opcodes and other instruction
attributes. Traditional methods randomize instruction fields
sequentially, which often results in verbose, redundant code and limited
control over distributions.
In this article, we explore using a hierarchical constrained-random
approach to accelerate generation and reduce memory consumption, while
providing optimal distribution and biasing to hit corner cases using the
Synopsys VCS constraint solver. We present and analyze the method and
discuss its effectiveness in today’s verification environment.
To access the full article (PDF
Format), click here.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.