The benefits of FPGAs over ASICs become more and more compelling as rapid-process technology scaling and innovation provides ever-greater speed, density, and power improvements. However, along with this technology scaling come other effects that previously could be ignored.
One of the accompanying effects of higher density is increased susceptibility to SEUs, which in turn causes soft errors. Although careful IC design and layout techniques have decreased the soft-error rate per bit at 65 nm and 40 nm, each process-technology generation offers twice the logic density, bringing with it a corresponding doubling in the number of configuration RAM (CRAM) bits.
A secondary effect of FPGAs becoming denser and more capable is that they now tend to sit at the heart of the system, often in the data path; this offers the designer an unprecedented level of system integration with Stratix series FPGAs. With this change, FPGAs are now a primary silicon choice for many systems, including those that fall into the high-availability category such as telecom, storage, and data-processing systems.
These application areas demand high reliability, and consequently, modern high-end devices, such as Altera’s 28-nm Stratix V FPGAs, must offer robust SEU mitigation including correction without any system downtime.
This white paper explains how the SEU mitigation enhancements developed for Altera Stratix V FPGAs provide a strong roadmap to address soft-error system challenges.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.