Editor's note: EE Times recently published a rebuttal by Ron Neale of Micron's assertions on the subject of phase change memory (PCM), together with some follow up comments. In response to a challenge from EE Times' Memory Designline, Ron Neale now provides our readers with some of the detail behind his rebuttal and his concerns for the commercial future of PCM.
The analysis I will describe here arose as a diversion from a project to define, for students, some low cost experiments that might allow them to make a contribution to phase change memory (PCM) scaling. What follows here is based on numbers obtained from the published literature, originality is only claimed for the analysis and its possible applicability.
The recent publicity and claims given for phase change memory (PCM) have scalability as the backbone. Among other misgivings, it was clear to this author that if PCM devices are to be competitive with other NV memory technologies and be a commercial success there are some serious problems that will need to be addressed.
A situation will arise where the active phase change material in a molten state (600oC) at the very core of the device would become highly constrained and in contact the dielectric and other parts of the device structure. The "mushroom" or "match-head" PCM device one of the proposed PCM structures was already operating with molten chalcogenide in contact with surrounding dielectric.
The PCM "link" or "gap" surface structure appeared best to offer the ability for experiments to evaluate the chemical reactions, diffusion effects and thermal properties of molten chalcogenide glasses in contact with dielectrics. The active region of the "link" device is already in contact and closely coupled to the dielectric on which it is fabricated.
A cursory examination of the literature both academic and popular gave considerable cause for concern. What the literature disclosed was that while the reset current of the link type PCM, that is the current required for transition from the low to high resistance state, was at reasonable levels for link devices, the calculated current density (J) for smallest cross section devices was very high.
A PCM prediction tool--a new direction
The thought occurred, that without the benefit of expensive and sophisticated simulations or calculations, it might be possible to use the results from the "link" structures as a prediction tool. A tool that would allow the reset current density to be predicted for PCM "link" devices with a square cross section, at dimensions where lithographic limitations made it impossible to actually fabricate the PCM devices. It might then be possible to further use this data and link it to the results that might be expected for cylindrical "pore" PCM structures at the photolithographic dimensions of 5nm to 20nm, needed for PCM to be commercially competitive. Although, working at the limit of any generation node of lithography square cross section apertures tend to become rounded, so it might be expected the results for the two structures would have a high correlation.
The initial step is shown in Figure 1. Where the value of current densities (J) as a function of the width (d) are plotted for "link" structures from two different sources. These results are sourced from the literature, (Ref 1) from the work of NXP and (Ref 2) the work of IBM. (In the latter case of IBM their actual experimental numbers were provided to this author). The thickness of the active material of the PCM "link" devices involved covered the thickness range of from 3nm to 20nm.
Figure 1: The curves of Current Density as a function of width for link structures.
Click on image to enlarge.
As shown in Figure 1, as the value of d is reduced to the point where d = t, (where t is the thickness of the link), the curves of J = f(d) converge on J values of 1 to 2x10E8 Amp/sq-cm. This immediately raises the question what happens to crystalline and molten chalcogenide when subjected to current densities at this level. Significant levels of electro-migration would be expected. The two sets of curves from different sources are positioned in relation to thickness in such a way that encourages a belief that these curves are a true representation of links in general.
This author is aware outside of his work on the development of PCM devices, and from other work with one-time programmable devices, "vias" and "anti-fuses", that current densities at the level cited above can, in a via, move tungsten into molten amorphous silicon (albeit assisted by alloying). There is little doubt that for one-time programmable Si-SiO-Si structures, current densities of the magnitude, predicted for 5nm to 20nm node PCMs, are capable of the physical movement of chunks of oxide in molten silicon.
The academic literature is sparse and has little to say on the effects of current densities of 2x10E8Amps/square-cm flowing in molten chalcogenide. We will return to that subject and its effects here later.
While the curves on Figure 1 can be extrapolated, they will in effect end when the link has a square cross section. At that point, and in a symmetrical thermal environment, the next experimental step will in effect create a thinner link standing on its edge. Therefore the curve of d =f(J) will move discontinuously to the higher current density of the family of thinner links.
Linking the square cross section values of the curves in Figure 1 will provide a line (curve) that it might be possible to link to cylindrical PCM "pore" structures, the cylindrical pore structures will be represented by a single curve. With the exception of the curve for the 20nm link device the square cross section end points are not clear or depend on extrapolation. Such a line can be constructed and has been added to Fig 1, it is a best estimate, all it suggests is that such a line would have a steep negative gradient.
Testing the predictions
Some might argue that the results from "link" devices have little to teach with respect to vertical "pore" PCM structures. The thought occurred that it might be possible to test the accuracy of any "link" to "pore" correlation by using all the results for PCM reset current values for vertical "pore" structures already available in the published academic literature.
These results were collected and added to the original "link" plots to produce Figure 2. The results are shown as an average curve and two curves on either side representing the extremes of the statistical distribution of the results.
Figure 2: The combined curves of Current Density as a function of width and diameter for link and pore structures..
Click on image to enlarge.
At this point, some words of both explanation and caution are in order. For these new curves the value on the d axis is now the diameter of the "pore" device structure. The inset diagrams in Figure 2 illustrate the two situations when the initiating molten core of the reset process is highly constrained and another (right) where it is not. Where a particular author provided the actual current density, that value was used, for others where only reset current value was provided the (J) value was calculated using the lithographic node of the process as the diameter of the pore. If sub-lithographic fabrication techniques were in play then the current densities would larger than those calculated and shown.
It is worth noting that for a set of perfectly insulated devices the characteristics would trace a horizontal line on Fig 2, i.e. constant current density. (Not a practical device if rapid quenching is required)
The statistical spread in Figure 2 is accounted for, in part, by the fact that different dielectric materials and structures are used, i.e. thermal engineering. Or the reset, current may be low because the devices were only lightly set into the low resistance state and therefore required a lower reset current. Not considered a reliable mode of operation.
The new curves of (J) converge with those for the "link" devices at lithographic dimensions of 5 to 2xnm. This author would venture to suggest at this is the level of current density, the reliability of a PCM, or for that matter any other active or passive electronic component associated with it would be questionable. It begs the question regarding the realistic future of PCM.
This also again makes the question of what happens in molten chalcogenide at 600 C at current densities of 1 to 3X10E8 Amps/sq-cm in the context of device structures even more important to resolve.
The next and important step in this PCM current density exploration story was from a need to increase the number of data points in Figure 2.
The additional results were collected from the literature and added. The last broad brush point added to fig 2, the brown ellipse, is an estimate by this author of the reset current density for the 45nm 1G-bit PCM demonstration device produced by Numonyx/Micron
The results from the work of Cho et al (Ref 3) at Samsung produced a surprise and a result contrary to what might have been predicted. For at least two sets of similar families of devices the reset current density of the devices trace the two straight lines shown on Figure 2 and appear to be going against the expected trend of higher current density with decreasing dimensions. The lower straight line extrapolates in a very encouraging direction for those with any concerns regarding PCM current density problems. The value of (J) is decreasing with decreasing lithographic dimensions. Extrapolation of the line of particular interest, the lower of the straight lines in Figure 2, would suggest that for PCM devices with lithographic dimensions of 5nm or less the value of reset current density would be 5 x 10E6 Amps/sq-cm. Does this mean there are no problems and why the apparent contradiction??
Current density problems solved? Not quite!
In order to provide what this author believes is an explanation of what appear at first sight to be very positive results in terms of reducing current density, it is necessary to return to the "link" structures.
For the purpose of simplification and explanation, Figure 3 is a supposed plot of two of the many possible link structures with different values of film thickness, the solid lines. Each has associated with it a second current density curve (dotted and color matched in Figure 3) of a device of similar thickness, except that the electrodes are further away from the active core of the link. That is the links are longer and less well cooled by the electrodes. This reduction of reset current for "link" structures has been reported in the literature (Ref 2) for a longer links.
Figure 3: A simplified diagram to explain the idea of device thermal design space..
Click on image to enlarge.
In Figure 3, as discussed earlier, as the cross-section of the link becomes square, the curves are shown to turn vertically upward in a discontinuous manner. That is, they in effect become thinner links turned on one edge. Again here a line can be drawn connecting all the square cross section devices of different dimensions. The same is also true for the dotted curves, the two lines are shown as yellow solid and dotted yellow respectively on Figure 3.
In Figure 3 the blue line provides what this author considers is the explanation of the work of Cho (Ref 3) and account for the straight lines in fig 2. The blue line in Figure 3 traces a series of square cross section PCM link devices of progressively increasing length with reducing width, i.e. thermal engineering. The space between the two yellow lines might be described as the PCM thermal engineering design space, it has limits. What Cho et al appear to have done is fabricate a family of devices with increasing aspect ratio of length to diameter. With this approach a point is reached where any further increases in length will have very little thermal benefit. From then on further reductions in lithographic dimensions will follow the general trend to higher current densities of Fig 2 and illustrated as the upturned blue line in Fig 3. For a cylindrical vertical "pore" structure the same thermal design space will be available.
In the limit high aspect ratio devices may extract a process yield penalty. However, they may have one advantage, especially if only the central core of the constrained device is switched with crystallized material acting in part as electrodes. With any permanent crystallization, a PCM reset failure, of the core region as a result of electro-migration composition changes, the active region can move along the device. This will have the effect of increasing the write/erase lifetime and may explain some of the recent claims for w/e lifetime improvements.
Problems and Electro-migration effects
Those of us, ref 5, who developed and worked with earlier generations of thin film PCM devices, had the luxury of working with a highly resilient PCM device. Key to this resilience was the simple fact that with the chalcogenide in the molten state the two terminal characteristics of the PCM showed constant voltage V-I characteristics. Over driving the reset current, merely expanded the molten region without any changes in current density. The current density was of the order 10E6Amps/sq-cm, or less, the two terminal characteristics were constant voltage. For the most part those devices were manufactured with the chalcogenide in its high resistance amorphous state and not all of the area of amorphous material was switched. The expanding and contracting molten state floated in a field of amorphous material. Nowadays, PCM devices are manufactured with the active material in its crystallized or low resistance state. In a highly constrained device all of the active material is switched. In the "mushroom" or "matchhead" structures the crystallized material forms a spherical device electrode.
The earlier generations of PCM devices were not without problems; even the effects of electro-migration were apparent. At the time it was safe to predict that with the smaller devices possible at the nodes of future generations of photo-lithography, the reset current and the on to off state of the memory would scale. Current density would not be any greater problem than it already was when the predictions were made and, therefore, was not a concern.
Sadly, the recent PCM publicity focused on scalability without benefit of a product and chose to ignore current density as a potential limiting factor. Without a serious product, the latching promotional efforts onto something that was true in the past, but may not be true in the future has proved to be very counter productive. As was considering the main competing technology, Flash, a fixed target.
From the results presented here earlier, the problem of current density and the link of PCMs of the past with today's reality is summarized in simple terms in Figure 4.
Figure 4: The simple difference between past prediction and today's reality..
Click on image to enlarge.
The PCM reset process starts with a very small spherical region at the core of the device becoming molten at about 600 C. This is called the initiating molten hot spot. From then on in the reset process positive feedback expands the molten region until it encompasses all the material that needs to be reset.
With respect to scaling, as long as the initiating molten hotspot is deep inside the PCM structure and the thermal environment is roughly constant then predictions of scalability are relatively safe and current density effects can be ignored.
Problems start to occur when the thermal environment directly impacts the formation of the initiating molten hot spot. This is the situation as device dimensions reduce and the hot spot size is formed in a reduced volume of material. The material available for raising the temperature is decreasing at a rate faster than the surface area that is cooling the region where the molten hot spot is trying to form. For a sphere the volume reduces as the cube of the radius (r3) while the surface area is reduces as r2. The situation is resolved by increasing the current density.
Figure 5 is a simple illustration of this problem. As scaling progresses the reset current (i) Amps reduces. As the limit of the present generation of photolithography is reached, current density (J) A/sq-cm starts to increase and that presents a number of potential reliability problems and jeopardizes predictions.
Figure 5: The initiating hot spot and the barrier to progress..
Click on image to enlarge.
Table 1 provides more details of the composition of the barrier that is illustrated in Figure 5. It is the problems that must be solved if PCM is to progress into the 5nm to 20nm regime, some directly associated with electro-migration others not. It is a barrier that must be removed or bypassed in order to produce PCM devices that are competitive in price, performance, bit density and reliability with competing and established memory devices. In fact to be just competitive may not be good enough.
Table 1: The list of PCM scaling problems that form the barrier.
Click on image to enlarge.
From the data presented here this author has the view that there is still much work to be done and many difficult challenges for those attempting to bring competitive PCM arrays to the market, they may or may not succeed. It may not be possible to break down the barriers that now stand in the way of PCM progress.
To construct devices that operate at current densities in the range 10E7 to 10E8 Amps/sq-cm and not account for what happens when currents at that level flow through molten chalcogenide or ignore it, is at best blind flying. Pretending there are no problems is not good enough. Promises of competitive products that are always just over the horizon or delayed, is not good enough. Relegating promised PCM array products to mere demonstration vehicles when they do not reach product status, is not good enough. Discussing esoteric devices and claiming applications with flights-of-fancy architectures, without a product, is not good enough. Putting old devices in new packages as ground bait to create demand, is not good enough.
All of the above have lead to PCM skepticism and in some case even worse name-calling. If PCM is ever to make progress and ever be considered as a serious and competitive memory product changes in approach are needed-after 40 years in development, time may be rapidly running out.
Ron Neale, CPhys, MinstP, is a former editor-in-chief of Electronic Engineering and coauthor of "Nonvolatile and reprogrammable, the read-mostly memory is here," by R.G.Neale, D.L.Nelson, and Gordon E. Moore, Electronics, pp56-60, Sept. 28, 1970. He was also senior scientist at Harris Semiconductor, where he was responsible for the PCM development program.
- NXP- Phase change memory technology, By Rob Wolters, NXP, Sept 2008 (PC_RAM_college.ppt)
- IBM-Y. C. Chen, et al., Ultra-Thin Phase-Change Bridge Memory Device Using GeSb, Y. C. Chen, et al International Electron Devices Meeting, San Francisco, CA, December 1-13, 2006, pp 777-780. Also: Phase-Change Random Access Memory: A Scalable Technology, by S. Raoux et al, IBM J. RES. & DEV. VOL. 52 NO. 4/5 JULY/SEPTEMBER 2008, page 465.and private correspondence.
- Highly Scalable On-axis Confined Cell Structure for High Density PRAM beyond 256Mb, By S.L. Cho et al. Proceedings IEDM 2005.
- "Nonvolatile and reprogrammable the read-mostly memory is here," By R.G Neale, D.L.Nelson, and Gordon E Moore, Electronics, September 1970.