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System Verilog configurable coverage model in an OVM setup – concept of reusability

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Methodology Makes Verif Easy
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re: System Verilog configurable coverage model in an OVM setup – concept of reusability
Methodology Makes Verif Easy   9/30/2011 5:28:42 AM
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Hi Parag Goel, Thanks for posting your artcle. I was in a assumption that we cant use a particular coverage related coverpoint in another coverage but your article explains it is possible and also thanks for providing the sample code. I will follow these steps in my next assignment.

paraggoel
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re: System Verilog configurable coverage model in an OVM setup – concept of reusability
paraggoel   8/28/2010 9:00:36 AM
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Hello Arno, Gud to see u liked the article. Actually, we at Applied Micro deployed SV & OVM only and e is not the language that we use here.So providing a comparision....??? Also, as described in the paper we discussed a whole of things of which all are practically coded. As far as number of lines are concerned they are very minimal as we have used macros extensively. But to tell you the fact, although a lot was coded but owing to the modularity of the approach that we took, it is very easy to modify & maintain the code.

Arno Nymous
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re: System Verilog configurable coverage model in an OVM setup – concept of reusability
Arno Nymous   8/27/2010 2:20:20 PM
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Hi Parag and Sakshi, thank you for this nice article. I would like to point out a few things about SV. SV by itself does very little to support an efficient means for functional verification. Adding the OVM (now UVM) actually makes this HDVL usable. The OVM however has been developed from the eRM. The eRM has been around for a while now and has been developed around the HVL e. I would like to see a comparison of SV and e functional coverage constructs. Also, working with both languages, I would be interested in hearing how many lines of codes have been written in both languages. Thank you and best regards.

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