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How to achieve 1 trillion floating-point operations-per-second in an FPGA

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Max The Magnificent
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re: How to achieve 1 trillion floating-point operations-per-second in an FPGA
Max The Magnificent   9/16/2010 8:36:11 PM
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Alex -- is that you? I haven't seen you for ages -- how are you doing -- I remember that paper -- I recommend other folks to read it also -- regards -- Max

unu
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re: How to achieve 1 trillion floating-point operations-per-second in an FPGA
unu   9/16/2010 7:59:52 PM
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The Altera people deserve congratulations! A 2008 web published paper available at alex.zamfirescu.googlepages.com/Zamfirescu_2008.pdf highlighted both the advantages of variable precision and of mixing the fix and float formats, skipping normalization until really required, etc. Altera people went on, and really did it. Bravo Altera! The extra innovation to keep mantissa in two's comp., instead of sign and mag., was not even predicted then. However, the paper described also the HDL extensions and what was feasible at that time in VHDL, and especially in Verilog. Maybe, people will pay attention and focus also on bringing HDL standards, to the level where designers could use them to push progress of FP computations (instead of confusing the execution machine FP formats with the designed FP capability).

Yankee
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re: How to achieve 1 trillion floating-point operations-per-second in an FPGA
Yankee   9/15/2010 4:34:38 PM
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The key is "how many seconds do you have?" In order to achieve faster response to demanding operations such as 3D transformation, speech recognition, radar processing, image analysis, and the like, more flops are needed, so the answer is found in the market requirements for products.

Max The Magnificent
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re: How to achieve 1 trillion floating-point operations-per-second in an FPGA
Max The Magnificent   9/14/2010 8:55:43 PM
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OK, the next question is how many floating-point DSP operations do different applications require to perform per second ... does anyone know any metrics here?

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