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How to achieve timing closure in large, complex FPGA designs

9/21/2010 08:40 PM EDT
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cuongpnguyen
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re: How to achieve timing closure in large, complex FPGA designs
cuongpnguyen   1/20/2012 10:33:42 PM
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Great article outlining the methodology. There are many ways to achieve timing closue and certainly the methods mentioned will work and will be complementary (ie. floor planning, incremental compile, realistic constraints, etc..). From the designer standpoint there are a couple more that I'd suggest. Use one-hot encoding for FSM, partition the FSM to 16-ish or less states, pipelining (which introduces latency but increases F(max)), minimize the use of ILA (Internal Logic Analyzer - such as ChipScope or SignalTap), capture fast protocols at the input boundary then fan out to "wide" logic (so you can use slower clocks) in the middle and use fast serializers at output boundaries. You'd also need to understand the architecture of the resources you're designing with (ie. 5-input LUT, ALM, etc..) to write code accordingly to avaid wide combinational blocks (ie. decoders, muxes, etc..). Everyone has a different style of designing and coding but a combination of the above (and understanding the methodology from this article) should help them select the right implementation.

xjordanx_#1
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re: How to achieve timing closure in large, complex FPGA designs
xjordanx_#1   9/29/2010 11:39:58 PM
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Of course... Altera need to promote "logic lock" because it's a unique feature of their software. The idea is nice but I have to agree - realistically every design is different, and the place and route tool usually does a better job without being constrained by pre-fitted blocks.

davewooff
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re: How to achieve timing closure in large, complex FPGA designs
davewooff   9/24/2010 9:34:36 AM
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"You should deploy an incremental design methodology." Speaking from experience as an engineer working on large Stratix III projects, I wasted a lot of time going down this avenue. I have since found that I can only achieve good results and efficient use of the device resources by having a single partition and letting the fitter get on with it. It may work for some applications but not necessarily in all cases.

Max The Magnificent
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re: How to achieve timing closure in large, complex FPGA designs
Max The Magnificent   9/21/2010 9:12:59 PM
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Quite apart from anything else, the *Basics of Timing Analysis* section presented on page 2 of this article will be useful for lots of folks.

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