This article features an example chapter from a new *Hot-off-the-Press* book on FPGA Design that just recently hit the streets in August 2010. This chapter is reproduced here with the kind permission of the publisher – Springer.
This book -- FPGA Design: Best Practices for Team-Based Design -- describes best practices for successful FPGA design. It is the result of the author’s meetings with hundreds of customers on the challenges facing each of their FPGA design teams.
By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed.
This book’s content has a strong focus on design teams that are spread across sites. The goal being to increase the productivity of FPGA design teams by establishing a common methodology across design teams; enabling the exchange of design blocks across teams. Coverage includes the complete FPGA design flow, from the basics to advanced techniques.
The author – Phil Simpson – is Altera’s senior manager for software technical marketing and product planning. In this role, Phil is responsible for Altera’s Quartus II software and third-party EDA interfaces product planning and the creation of the Altera design flow software roadmap. Phil holds a BS (with honors) in Electrical & Electronic Engineering from City University, London and an MSC (with distinction) in system design from the University of Central England, Birmingham, England.
CHAPTER 12: TIMING CLOSURE
12.1 Timing Closure Challenges
Timing Closure is the area of the design flow that can cause the most frustration to FPGA designers. This is the area which can eat up the compute cycles on your workstation, it can result in feature drop from your system design and may result in you having to pay for a faster speed-grade device than you intended to use.
Most of the chapters in this book have revolved around preventing timing closure challenges in your design. This chapter presents moves onto the next stage by presenting a design methodology for achieving timing closure.
So, why is timing closure a challenge in FPGA designs?
Over the last decade there has been a huge increase in the FPGA device density and the size of the designs targeting FPGAs. FPGA device logic density has increased by approximately 30X, and the amount of embedded memory has increased by approximately 70X. Over the same period of time, the speed of workstation CPUs have only increased by a factor of 14. All of these create a compile time challenge for high density FPGA designs.
On top of this, the clock speeds of the designs and the interface speeds have risen substantially. Today’s devices include transceivers that can reach speeds of more than 11 G and DDR III memory interfaces that run in excess of 533 MHz.
These types of applications require more complex timing constraints such as source synchronous interfaces and inter clock transfers.
The process geometries of modern FPGAs now dictate that timing analysis be performed at two or more timing corners in order to guarantee timing closure. At these smaller process geometries the delays are typically dominated by the delays of the interconnect routing as opposed to the cell delays. This creates a challenge in the placement of the design to avoid long interconnect delays whilst avoiding routing congestion.
The addition of dedicated hardware blocks, such as embedded memory and DSP blocks provide the benefit of increased functionality, but can create a challenge in placement with relation to the logic that interfaces with these blocks.
The good news is that the FPGA vendor software has risen to the challenges and includes a number of features to solve these challenges. In many cases, the default settings will meet your performance goals push-button. For the designs that do not meet your goals there are a number of analysis tools and features to enable you to succeed.