Editor's Note: This article is reproduced from the Xilinx Xcell Journal with the kind permission of the folks from Xilinx.
In the current era of communications and information technologies, automatic biometric personal recognition systems represent the state of the art in high-performance signal- and image-processing applications. In fact, it is not difficult to find in our daily lives systems requesting our personal authentication/identification before allowing us to use them; electronic tellers, computers, mobile phones and even cars require such authorization. Many end-user applications that demand better levels of security than PINs, passwords or ID cards use personal recognition algorithms based on biometric (physiological or behavioral) characteristics, usually delivering them as a kernel.
As a proof of concept, we developed an automatic fingerprint authentication system (AFAS) on the second smallest Xilinx FPGA device in the Virtex-4 LX family, making use of the Xilinx Early Access Partial Reconfiguration design flow and tools. The experimental results demonstrate it is possible to embed a full, highly demanding biometric recognition algorithm in such a small FPGA at an extremely low cost, processing it in real-time while preserving data accuracy and precision in its physical implementation by multiplexing functionality on the fly over a reduced set of resources placed in a partially reconfigurable region (PRR) of the device. These promising results, together with the proven maturity of the technology we used, encourage us to move this solution from research to industry, in an attempt to make partial reconfiguration (PR) available to the consumer world in the way of secure commercial products.
Basics of Biometrics
Computationally complex applications processed in real time, driven at low rates of power consumption and synthesized at low cost are unavoidable requirements today in the design and development of embedded systems, particularly when addressed to mass-production niches. In this context, dynamic partial self-reconfiguration of single-context FPGAs arises as a firm technological alternative, able to deliver a high functional density of resources to efficiently balance all those demands for time-, power- and cost-sensitive applications.
Software-defined radio, aerospace missions and cryptography are some of the known applications that exploit the benefits of dynamic partial reconfiguration of programmable logic devices today. In this context, our group is applying PR to an application space that hasn’t traditionally leveraged it: biometrics. As security has become a major issue in today’s digital information environment, especially for application fields like e-commerce, e-health, e-passports, e-banking or e-voting, among others, we believe the use of PR in biometrics holds great promise.
However, biometrics is complex. It requires stringent and computationally intensive image/signal processing in real time, along with a great deal of flexibility. In addition, personal recognition algorithms are in continuous evolution. As the research community expends major effort in this field, error rates like false acceptance and false rejection are improving. As a consequence, consumers are growing more confident about biometric systems, and acceptance is increasing. Given that progress in biometrics technology is expected to continue in the future, biometric products already in the market will have to admit upgrades in the field just to avoid getting obsolete, and for this they require open system architectures. In this regard, the flexible hardware found in run-time reconfigurable FPGA devices enables the versatility and scalability needed.
Finally, cost-effectiveness is probably the most important reason for biometrics to make use of partial reconfigurability. In aggressive markets like consumer electronics or automotive, vendors must market their systems at a competitive cost. Customers demand products with the highest level of security at the lowest possible price point.
The way to improve security and reliability is by increasing the computational power of the biometric recognition algorithm. This increment of computation usually involves a like increment in execution time and also in cost (resources). However, the cost is hardly affected in those scenarios where the design is based on dynamic-partial-reconfiguration technology. Using PR, designers can partition that new computation and schedule it as new processing stages added to the current sequential execution flow of the application. Thus, cost often can be held invariant to functional changes of the algorithm.
Designers can partition the biometric recognition algorithm into a series of mutually exclusive stages that are processed sequentially, where the outputs or results of one stage become the input data for the next. This sequential order means designers can multiplex hardware resources in time and customize them to execute a different task or role at each moment, increasing their functional density and thus keeping constant the total number of resources needed to process the entire algorithm. Moreover, the reconfiguration overhead is short enough so as not to eclipse the benefits gained by hardware acceleration.
Furthermore, reconfiguring one set of resources on the fly will not interrupt the rest of the resources available in the FPGA. In this way, the resources that are not reconfigured continue to operate and guarantee the link with the exterior world for the entire life cycle of the application.
Our challenge in this work consisted in demonstrating that PR fits well in the development of complex personal recognition algorithms based on biometric characteristics, making use of a two-dimensional design abstraction level through which the functionality is managed not only in space but also in time. We describe this target step by step in the next sections.