The automotive industry is rapidly adopting intelligent image processing to synthesize information from multiple periphery camera sensors, effectively giving vehicles the ability to 'see' and 'recognize' their surroundings. This trend is driven by a common goal of manufacturers to create a completely safe driving environment. For example, Volvo has the “Zero-by-2020” goal states that no one will be killed or injured in a new Volvo by 2020.
CogniVue image cognition processors (ICPs) with APEX technology enables image cognition in the next generation of intelligent safe vehicles. ICPs provide real-time embedded image and video analytics applications for emerging on-board intelligent vision systems such as: Enhanced backup camera with object detection and image dewarping, lane departure warning, blind spot monitoring, traffic sign recognition, collision avoidance, driver monitoring, and surround view.
APEX, programmable parallel technology
At the core of CogniVue ICPs is APEX, a technology suited for compute intensive image cognition and processing operations. APEX integrates various programmable resources including a massively parallel single instruction multiple data (SIMD) core, a RISC processor, DMAs devised for efficient data movement, and a sequencer that efficiently orders operations to maximize efficiency.
APEX is multicore and combines the SIMD array processor unit (APU), to execute all the low level parallel operations inherent in image cognition and processing algorithms, with a RISC core to process non-parallizable processes and manage algorithm execution. Application level program routines run completely independently from APEX, on a second RISC core.
APEX is scalable, thus increasing the parallelism of the APU by adding more processing elements (computational units with dedicated memory) boosts the processing capability linearly. In addition to increased performance, maximizing the parallelism permits operating at lower clock speeds thereby reducing power consumption and heat dissipation. The processing elements are made up of computational units (CUs) and dedicated co-located memory. Co-locating the memory with the CUs maximizes the benefit of data locality and ensures data transfers to off chip memory are minimized, greatly reducing power and increasing processing performance.
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(Story courtesy of Automotive Designline Europe.)