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DSP options to accelerate your DSP+FPGA design

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arun5500
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re: DSP options to accelerate your DSP+FPGA design
arun5500   10/29/2010 2:38:52 AM
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Hi ,This is Arunraj an master graduate in VLSI Design,Iam doing my acadaemic project in designing an DSP ip ,thanks for this valuable post,can you upgrade me by providing some more valuable details of DSP in FPGA design.my mail id is mbrsai.me@gmail.com,thank you in advance.

Abrahim
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re: DSP options to accelerate your DSP+FPGA design
Abrahim   10/26/2010 7:43:33 AM
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one important aspect of a DSP-FPGA combination which was left out of this article but can be very important is the use of FPGA as a 'merging' or 'connecting' pool for data and communication between DSP/Processors. Often in critical applications it is desirable to avoid the task scheduling complications and the glitches & overheads associated with a RTOS framework. in such a scenario small processors dedicatedly executing critical tasks and using the FPGA as an entity to exchange data and communicate with other processors help to keep the architecture simple and robust. in addition to serving as a data sharing location it can also takes care of arbitration and data aging related operations. I also found it very helpful in interfacing ADCs (even those with complex interfaces) to DSPs using FPGAs as it even took care of some pre-processing filtering needs. As a fundamental rule of the thumb i normally shift 'static' logic into the FPGA ans 'configurable/dynamic' logic into the processors, and on many occasions it has helped me use smaller DSPs with better results.

patrick.mannion
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re: DSP options to accelerate your DSP+FPGA design
patrick.mannion   10/21/2010 4:02:46 PM
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Hi Teddy: Thanks for pointing that out! I've updated the file so that when you click on those images they'll enlarge for you. Best regards,

teddy_zhai
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re: DSP options to accelerate your DSP+FPGA design
teddy_zhai   10/21/2010 2:35:37 PM
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the Figures in the first are too small and not readable.

DrFPGA
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re: DSP options to accelerate your DSP+FPGA design
DrFPGA   10/18/2010 5:25:13 PM
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One point left out of this overview is the importance of feeding data to high performance DSP algorithms. Many times the bottleneck turns out to be the off-chip memory interface when doing a high-performance FPGA-based DSP design. Sparce matrix operations in particular can be a challenge. How about addesssing this point in a future article?

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