Serializer/Deserializer (SERDES) models are traditionally available as transistor-level models that use proprietary encryption algorithms and are simulation platform dependent. While these models provide maximum accuracy to simulate the linear and nonlinear parts of a digital system, due to limitations in simulation speed and the inability to be ported over different electronic design automation (EDA) platforms, they prevent users from accurately predicting low bit-error-rate (BER). With increased data rates, reduced voltage levels and low BER requirements, the semiconductor industry has now created a new standard for serial link analysis to overcome the limitations of transistor-level models. The standard, IBIS AMI (Algorithmic Modeling Interface), defines an interface between AMI models and EDA tools. Its popularity stems from the fact it allows vendors to include their own proprietary algorithms without any dependence on a specific EDA platform. IBM originally pioneered AMI model generation and, today, remains one of its main driving forces.
As the name suggests, IBIS AMI models are a hybrid of analog and DSP models. The I/O front end of the IC is assumed to be a linear, time-invariant analog representation controlled by the regular IBIS model to account for impedance mismatch between the driver/receiver and interconnect models. The IC’s back-end signal processing functionality that performs pre- and post-conditioning of signal is achieved using an algorithmic/behavioral representation of the device. The main advantages of using this technique are that time-domain simulation of nonlinear time-invariant TX/RX models can be performed much faster and, when a linear, time-invariant representation is used for SERDES devices, statistical simulation techniques can be utilized to predict low BER. Though many EDA vendors have long provided analog and DSP co-design platforms, due to the non-existence of a standard, portable SERDES models have not been available from semiconductor IC vendors.
IBIS AMI models are primarily used to predict a serial link’s performance with an eye diagram and BER. In a serial link, transmitter and receiver blocks can utilize various types of equalizers including clock and data recovery circuitry. In an AMI model, this can be effectively represented at the behavioral level utilizing C/C++. Because AMI models are compiled C++ models they cannot be reverse engineered and are, therefore, protected. Consequently, semiconductor vendors can control what details of their IP is exposed to the user, allowing them to freely distribute these models for a wide variety of EDA tools.
The IBIS AMI specification defines the required interface/communication protocols between a SERDES model and an EDA tool and allows the designer to successfully simulate a SERDES model irrespective of the EDA tool. Because most of the ongoing efforts are targeted toward standardization of the communication interface there is not much literature available today on how to actually generate these models. As a result, many existing signal integrity (SI) tools are able to easily simulate these models, but the generation of these models remains a difficult task. In fact, it can take anywhere between 6 months to a year for a semiconductor vendor to create the in-house expertise needed to generate such models. This paper showcases a flow that can be used to generate AMI models. An example of a PCI Express Gen2 transmitter is used to help better explain how this flow works.
PCI Express TX specifications
Some of the key transmitter specifications include data rate, the transmitter (TX) equalization, logic levels, and jitter. Below are the basic TX specifications that will be used to create the PCIe TX topology:
AMI model representation
An important aspect the designer may need to consider is the number of samples/bit that is used to accurately represent a TX model. A good model should provide the flexibility to change the number of samples/bit during runtime, which means that component parameters like de-emphasis and wave-shaping filter should be tied to the data rate and sample interval. An example of this is shown in Figure 1. Here, a two tap de-emphasis is implemented in SystemVue, an electronic system level (ESL) product from Agilent Technologies’ EEsof organization. Instead of using a fixed-delay, this implementation gets the flexibility it needs to change the number of samples/bit during runtime using a variable/programmable delay.
Figure 1: In this implementation, the incoming signal is divided into two paths, scaled and then summed together to generate an output signal. A variable/programmable delay used in one of the signal paths provides the flexibility necessary to change the number of samples/bit during the simulation process. This variable delay provides a one-bit delay, irrespective of number of samples per UI.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.