The resolution of this issue has recently been much simplified through the availability of highly versatile mixed-signal devices that combine microcontroller, programmable digital logic and versatile configurable analogue circuitry onto a single device. An example of such a device family is Cypress's new PSoC3 (Programmable System on Chip).
When systemic 'shocks' happen, programmable microprocessor-based designs can quickly be adapted, since new code and new circuit boards can be spun so much more rapidly than new silicon. Sometimes, however, an application requires dedicated peripheral or processing support that hasn't yet been incorporated into any of the readily available microprocessors. First solutions to new problems of this nature can end up as 'bitty' combinations of microprocessors with FPGAs, PLDs and various dedicated fixed-function chips that are often only half-utilized to implement some specialized but required behavior. The resulting large circuit boards and inefficient BOMs can threaten to snuff out a nascent new market.
Highly programmable system-on-chip architectures offer an alternative approach. In such devices, chip design effort is initially devoted – often without a clear picture of specific usage scenarios – to creating a more configurable, more flexible architecture, on both the analogue and digital sides. Digital flexibility comes from including blocks (Universal Digital Blocks, or UDBs) that can implement complex combinatorial and sequential logic functions, independently of the main processor core. Dedicated coprocessors for frequently encountered generic signal processing tasks such as filtering can also be included.
On the analogue side, the ubiquitous op-amps and comparators can be enhanced with a rich network of switches and on-chip components, to deliver a range of analogue blocks whose interconnection is limited only by users' imaginations. Flexible multi-domain clock trees add a further layer of versatility.
These highly versatile devices can't always match the raw silicon cost of dedicated, single-function devices. However, as soon as something slightly different is needed, the programmable device usually offers the most competitive BOM cost, compared to the patchwork solution required from less flexible parts. And the rapidity of the product design – and redesign – process has ensured that programmable "systems-on-chip" have made a significant contribution to electronic product design in the past few years.
Programmable SoCs have already been proven to support all the elements required for a complete contemporary consumer music appliance requiring USB digital audio capability. The programmable digital logic and versatile clock capability deliver a no-external-components approach for generating the required audio master clock and synchronizing it rapidly and exactly to the incoming USB frame structure. The heart of the solution is the USB audio clock recovery process; the basic configuration used is outlined in figure 1:
Figure 1: Example USB audio clock recovery architecture
The flexible USB interface of a programmable SoC allows several audio and control protocol endpoint functions to be combined. The matrix of programmable digital logic blocks implements a frequency synthesis system that derives any standard audio sample rate master clocks exactly from a single stable crystal source. In normal operation, the clock is locked to the received USB timebase using the start-of-frame token pulse timing.
The system clock PLL is integrated into this synthesizer through the flexible clock routing framework. The whole system exactly tracks the source sample rate and delivers a high quality, audio master clock for the system's audio converters, at a jitter level that's commensurate with the needs of modern quality audio systems.
The audio data is typically clocked out of the buffer into one or more standard I2S interfaces with the required number of channels, implemented again with the programmable digital blocks. This interface can connect to a standard audio DAC, processor or 'digital amplifier'. Other custom interfaces can also be implemented in these blocks, for example, S/PDIF transmission. The whole process can operate bidirectionally, with data from an ADC being transmitted back out through the USB port.
Some USB audio modes require that the local clock is able to 'slip' against the incoming clock, for instance from a source that's relaying a remotely-synchronized audio stream. A programmable SoC architecture can run in an adaptive mode that finely trims the local clock to provide the required 'slip'.