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Rice University: Making memory out of silicon oxide

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resistion
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re: Rice University: Making memory out of silicon oxide
resistion   11/4/2010 4:59:07 PM
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Here is another one: 3886577, closer to the one in this article.

resistion
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re: Rice University: Making memory out of silicon oxide
resistion   11/4/2010 4:29:26 PM
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I found that this early expired patent US3540006 describes surprisingly well many ReRAMs explored today.

resistion
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re: Rice University: Making memory out of silicon oxide
resistion   11/4/2010 3:49:10 PM
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The filament can be made of anything, as long as it is localized and allows a mode of conduction. Just as nitride traps can hold charge for SONOS, MONOS etc., oxide traps or other defects can conduct current. Just like for charge trap flash, the trap defect density could be crucial. The problem I have with memory that is scaled down is too few electrons moving in and out or staying in one place. Noise is significant.

sharps_eng
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re: Rice University: Making memory out of silicon oxide
sharps_eng   11/3/2010 9:17:09 PM
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Is the filament a single-atom chain? Once the first filament is made, the forming potential collapses and no more filamentation can occur. To make multiple parallel chains you need individual switches for each chain (not space-efficient). To make chains rugged, the forming must be well-characterised to ensure each chain is 'properly' formed every time, otherwise thermal etc effects could cause it to go high-resistance. No opportunity for refresh like DRAM in a non-volatle memory, unless a pseudo-static approach is feasible. The advantage of the charge-based memory types is that you aren't relying on a single electron being in the right place at the right time (well, alright, on average you are :-); they are parallel-architectures not serial like this one. I'd love to hear more and understand how these issues are being overcome.

JanineLove
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re: Rice University: Making memory out of silicon oxide
JanineLove   11/3/2010 5:42:23 PM
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Editor's Note: I came across the authors' research on the ACS web site and contacted them to see if they were willing to write up their work for the Memory Designline. Happily, they agreed and have given us a glimpse into some of the research going on in resistance random access memory (ReRAM). Please read and share your comments.

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