While PCI Express (PCIe) has successfully penetrated business-focused market segments -- graphics, storage, servers, communications, and embedded systems - lesser known is its rapidly emerging growth in the consumer market. WiFi modules, set-top boxes, cable modems and home gateways now feature PCIe, and both the volume and number of product types are growing by leaps and bounds. This segment is both price- and power-sensitive, necessitating highly efficient designs. And with many CPUs coming with just one PCIe lane, designers unwilling to limit a product's performance and efficiency are taking an innovative approach: fanning out from the CPU to multiple peripherals, through a new generation of PCIe switches.
This article will look at the options designers have in PCIe interconnect and help them maximize both performance and power efficiency of consumer-electronics designs. It will illustrate how that efficiency is achieved by taking advantage of PCIe switches' flexible ports and lanes, small packages and unique ability to fan out to a number of endpoints.
From its debut in 2004, PCIe has penetrated every market segment -- not the least of them consumer electronics, with graphics cards, add-in cards and motherboards. Yet even after that success, there has been one portion of the consumer market segment that to date hasn't adopted PCIe - home gateways, set-top boxes and cable modems. This was primarily because the processors used in this market were either PCI-based or the manufacturers used their own ASICs with proprietary buses.
All that's changing now, primarily because the SoC vendors have realized that they can now add one lane of PCIe 1.0 (Gen 1) at 2.5Gbps and save significant space by removing 64 pins of PCI in their packages, enabling them to offer more cost- and function-optimized devices. Also, since PCIe has been around for more than six years, the cost structures have now come down to a point where it makes economic sense to utilize this interface. Furthermore, the ecosystem is huge, which makes connecting to PCIe processors and endpoints extremely easy. Last but not the least is the emergence of endpoints based on the latest complementary interconnect technology such as USB 3.0, whose bandwidth requirements are supported by PCIe Gen 2 (5.0Gbps) PCIe.
In addition to the above trends, another is the use of a PCIe switch to fan-out the connectivity to multiple endpoints such as WiFi radios, USB 3.0, Gigabit Ethernet (GbE), and SATA 6G. Since the processors in these markets have only one PCIe lane, a PCIe switch optimized for this market ensures connectivity to the large number of endpoints. Let's take a look at some of the usage models in these applications driving the need for a PCIe switch.
In this usage model, the dual-band WiFi radios are connected to the CPU via a PCIe switch, thus extending the connectivity of the processor to dual-frequency WiFi radios - 2.4GHz and 5.0GHz. This enables vendors to offer one WiFi radio for data access and the other for high-bandwidth video access. For designers worried that the bandwidth between the processor and the PCIe switch could be a bottleneck, the PCIe switch offers a x2 configuration if the processor also supports it, as shown in Figure 2.
In figure 2, since the connection between the processor and the PCIe switch is now x2 wide, the bandwidth between the processor and the WiFi radios is perfectly balanced with no bottlenecks in the system. Along these lines, another usage model is a bandwidth bridge.
In this usage model, the PCIe switch is not only providing fan-out connectivity but is also acting as a bandwidth bridge. The connection between the processor and the PCIe switch is a x2 wide Gen 1 (2.5Gbps) interface, while the PCIe switch is fanning out to Gen 2 (5.0Gbps) endpoints such as USB 3.0 and SATA 6. In this usage model designers may be worried about the bandwidth bottleneck between the processor and the PCIe switch, as it is 5Gbps, while the bandwidth between the PCIe switch and the endpoints is 10Gbps. Figure 4 illustrates a usage model that eliminates such concerns about bandwidth bottlenecks.
In this usage model, the bandwidth between the processor and the PCIe switch and between the switch and the endpoint is 5Gbps - a perfectly bandwidth-balanced system.In the set-top box market, designers need to build in more fan-out connections to a WiFi radio, USB 3.0 endpoint and additional GbE port, as shown in Figure 5.