Optimized for short distance (<10cm) but suitable for long-distance (m)
Huge range of speed requirements: ~10Mbps to ~6Gbps
Power efficient throughput adaptation using burst-mode
Clocking: shared or non-shared reference clocks
Independent of foundry process
Multiple transmission modes for better power efficiency
Multiple transmission speed ranges/rates for varied application needs and for mitigation of interference problems
Fixed transmission rates for high-speed mode but flexible for low-speed modes within specified ranges
Multiple power saving modes, where power consumption can be traded-off against recovery time
Symbol coding (8b/10b) for spectral conditioning, clock recovery, and in-band control options for both PHY and Protocol level
Configurability to reduce cost and tuneable for best performance
Since the M-PHY is meant to replace the D-PHY in applications that require higher throughput, systems designers will have a choice as to which physical interface to use. Table 1 highlights the differences between the D-PHY and M-PHY, and Figure 1 shows the location of the camera /and display subsystems linked by either the D-PHY or M-PHY interconnections.
Figure 1: Inside of a mobile phone showing an example of MIPI connections between the application processor and camera and display subsystems. Connections made using a D-PHY or M-PHY (source: Mixel, Inc.)
Table 1: Comparison of the characteristics of the MIPI’s D-PHY and M-PHY (Source: Den Besten, Gerrit of NXP)
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.