For about two decades, hardware designers have been trying to use high-level synthesis (HLS) tools. The primary goal of high-level synthesis tools has been to increase design and verification productivity by raising the level of abstraction and by defining the architectures using less code. In addition, the idea is to also reduce complexity and the number of bugs introduced due to human-error, increase simulation speed, and facilitate exploration of alternative micro-architecture choices.
This article describes the work done at Texas Instruments (TI) to research the suitability of the latest generation of HLS tools for hardware design. Particularly, the analysis is focused on C-to-Silicon Compiler from Cadence Design Systems. The findings will interest RTL designers and architects who might be considering adoption of HLS tools, methodologies, and flows.
Past experience with High Level Synthesis
At TI, multiple HLS technologies and tools have been investigated. These were based on C/C++, custom languages, as well as SystemC in recent projects. The limitations and challenges faced were manifold. Some tools focused either on control logic or data-path thus limiting their applicability. Others would have custom constructs or languages, making integration with existing flows inefficient. And in most cases, it was difficult to generalize the performance of a tool across various designs as tools gave different results on different designs – one tool could deliver better results than another on one design but would be worse on a second design.
In almost all cases, one advantage was noticeable – designs implemented at a higher abstraction level indeed accelerate the implementation process and reduce the occurrence of low-level implementation bugs that are routine in RTL code. It is also easier to quickly try different operating points for frequency and explore the tradeoffs – something that cannot be practically achieved in an RTL flow.
Requirements for adoption of HLS tools
Before HLS flows can be adopted in the mainstream, there are two major requirements for the technology to fulfill. First is the return on investment, and second is the maturity and ease-of-use of HLS tools.
1. Provide sufficient value to justify the costs of adoption
a. Equal or better than hand-coded designs in terms of quality of results in implementation
b. Order of magnitude improvement in design productivity
c. Equal or reduced verification workload
2. Maturity, ease-of-use requirements for tools
a. Help designer understand when a design is optimal
b. Unified/integrated solution for control and data-path
c. Extensive debug support and visibility into high level implementation
d. Tight coupling with industry accepted synthesis tools
e. Equivalence checking
f. Incremental synthesis for ECO
g. Clean RTL output
h. Ease of integration of structural components (memories, hard macros, etc.)