My original concerns with the ability of phase change memory (PCM) to scale to the sub 30nm lithographic nodes were directed principally at the problem of high current density and its consequences. A recent statement  and  has added new fuel to the PCM scalability argument, and it raised a new set of PCM scaling problems related to fabrication difficulties and power dissipation.
These new problems first appeared in a justification statement made as part of a patent application by some who are close to leading-edge PCM developments. Clearly, the purpose of the patent was to offer some new direction of development as a potential solution to the set of problems raised. This possible new direction for PCM structure will be explored in this article.
In Figure 1 (right-hand side is an artist’s impression of the newly proposed structure, in part cutaway), the active material is deposited as a sub-lithographic thin film on the sidewalls of a pore-like cylindrical aperture. This forms the active material into a tube, with the center of the tube back-filled with dielectric. At the bottom of the tube, the crystallized active memory material makes direct contact via an interface layer with a matrix selection device of the same diameter. The memory device acts as a "high aspect ratio" structure, with all of the thermal design advantages of that structure as was discussed in . That is, the design keeps the cooling effects of the electrodes away from the active region and minimizes reset power.
Figure 1: The Wrap Around Link (WAL-PCM) and its evolution. (Click figure for larger image.)
My view of how this new PCM structure can be considered a close relative and evolved from the "link," is shown in the structural evolution diagrams at the right of Figure 1. These show that this new structure is, in reality, a rolled up or wrapped around link-PCM (WAL-PCM).