JEDEC and ONFI have a collaborative effort underway to develop NAND flash specifications, with a goal to unify the industry and develop a standard which is backward compatible with existing flash interface technologies. Currently, work is underway to develop a common command set and packaging. A subsequent objective is to achieve both a common command set and compatibility for the data interface at the 400MT/s speed.
What’s involved in implementing DDR NAND?
Since there are basically only two flavors of DDR NAND today, toggle mode and ONFI, controller vendors have been able to support both types. The interface differences between the original legacy NAND, toggle mode and ONFI are actually relatively small. Besides the usual control signals: CE#, ALE and CLE, the chart below shows the addition of the DQS (data strobe) signal, and the use of a CK (clock) and W/R# (write/read direction) signal for the synchronous, or ONFI interface. The DQS signal is considered to be “source synchronous.” What this means is that it is driven by the device that is sourcing the data. In the case of a data write, data is coming from the host; therefore, the DQS signal is driven by the host. For a read, data is coming from the NAND flash; therefore, DQS is driven by the NAND.
There's been a lot of interest on the site for some back to basics articles, and I am on the look out for some new ones. In the meantime, thought this one from Toshiba seemed like something that might fit the bill.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.