An interface implies a protocol, and a protocol means time. So generally they fall under the category of control. Interfaces can be complex or simple and they can be custom or standard.
When timing is part of the interface behavior, such as with bus protocols, SystemC is the better choice. With protocols, you usually want to test how something is done: is it compliant. Therefore, you need to simulate and test the impact of the interface on the timing in the source description, because time is a property of protocols. Therefore, you should use SystemC. Because the protocol is hard coded in the source, you can test the consequence of a specific protocol in the source, and the HLS tool will not change it; it will build it how you tell it to.
Yet, for simpler interfaces, such as point-to-point connections found in processing blocks and processing pipelines, we recommend C++ because the goal is to make sure the transfer of data is “safe,” regardless of how it is implemented. In other words, all you care about is what it does. This does not have timing information and does not need to be simulated.
If you care only about the outcome, the what, you don’t want to redesign the interface in your own model. You simply pull from a library definition the interface implementation that fits your needs. Since you don’t have the actual protocol model in the source, the source behaves correctly. Thus, instead of committing to the interface in the source you wait to commit to it as you go through synthesis. This pure sequential ANSI C/C++ implementation preserves the ability to change from one interface protocol to another without modifying the source, resulting in less chance for errors and more time for exploring design space options.
An example system with a bus-based communication architecture is shown in Figure 1. The system contains a master and two slaves communicating through an AMBA 3.0 AHB-Lite bus. This example shows how to combine untimed functional descriptions with cycle-accurate interface protocols wrapped in Modular IO classes. In this example, the master is assumed to be the target for HLS. The rest of the components in the system are considered external, from a synthesis stand point. However, these external components exist in the testbench for verification.
The master and slaves communicate using Modular IO interface classes that abstract the protocol used for communication. The reason for this is to improve ease-of-use and design reuse. The master consists of three, two-way handshake interfaces and an AHB-Lite bus interface (bus I/F). The two-way handshake interfaces are: command interface (cmd in I/F), data in interface (data in I/F), and the data out interface (data out I/F). Depending on the commands received from cmd in I/F, the master would do one of the following: 1) read samples from data in I/F and write it to Slave 1 memory using bus I/F, 2) one at a time, read samples from Slave 1 memory using bus I/F, filter it using FIR filter, and write the result to Slave 2 memory using bus I/F, and 3) read samples from Slave 2 memory using bus I/F and write it out on data out I/F.
Figure 1: Bus-based communication architecture.
(Click on image to enlarge)
The master’s interface and port definitions are provided below:
Master1 uses the wait_in interface class to receive commands and data. It uses the wait_out interface class to send data out.
The sc_cthread process inside the master is provided below:
Figure 2 shows the advantages of using untimed C++ synthesis when only simple point-to-point protocols are required. The top-level C++ source contains only untimed C++ variables with no concept of interface protocol. The process of interface synthesis allows designers to specify simple, timed protocols as constraints during the synthesis process.
Figure 2: Using interface synthesis to add a timed protocol to C++ interfaces.