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How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs

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Max The Magnificent
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re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Max The Magnificent   1/18/2011 8:25:43 PM
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I don't know about you, but I think this is very, VERY interesting. I can think of all sorts of applications where the ability to implement one or more All-Digital ADCs in a purely digital FPGA would offer all sorts of advantages...

xjordanx_#1
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re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
xjordanx_#1   1/20/2011 11:39:57 AM
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Hmmm... reminds me of the 12-bit ADCs that Boss (Roland) used to implement in their audio effects units of the 1980's. Though they did not have an LVDS input (wasn't invented yet!) they used a 311 comparator instead, with an R-2R ladder. If you have enough pins and you are using a low-cost FPGA you could take the same approach, albeit with successive approximation, and not have to pay a royalty... :-)

martinm_de
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re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
martinm_de   1/20/2011 12:43:12 PM
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This is nothing new http://www.colognechip.com/asic/ip-cores/c3-codec-presentation_socip.pdf

WSFPGA
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re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
WSFPGA   1/20/2011 2:30:02 PM
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Many times the "new" techniques are the most old techniques, sorry Max but nothing new here, this solution coming being used with microcontrollers since many years; the most old App Note that I know was written by Motorola. ( Try Google,is very very old I don't remember the name ) I'm using this solution - implemented with FPGA - into several customers projects since several years. Walter

Max The Magnificent
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re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Max The Magnificent   1/20/2011 2:37:03 PM
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Bummer -- I was really excited -- but maybe they have a new twist -- I will ask them to comment -- Max

James.Ma
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re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
James.Ma   1/20/2011 3:50:24 PM
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The input voltage & current range is limited to what the LVDS buffer can handle. Not bad but it's not going to put ADI out of business.

mngardon
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re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   1/20/2011 4:51:24 PM
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Thanks for the comment! Stellamar IP does not require any external precision components. In other words we do not need an external DAC, R-2R ladder or comparator.

mngardon
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re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   1/20/2011 4:54:11 PM
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Thanks for the comment! Our All Digital ADC is very different than previous paper and claims, such as the one mentioned. We have better performance using a 10MHZ clock on several different FPGA families within Xilinx, Altera and Actel. We'd be happy to talk about it some more with you at any time.

mngardon
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re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   1/20/2011 4:56:20 PM
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We are unaware of this ADC technique and could not find the referenced paper in any of our research conducted over the last 2 years. Could you please provide additional information on this ADC implementation, such resolution, bandwidth and master clock.

mngardon
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re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   1/20/2011 5:04:42 PM
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Thanks for the comments everyone! We welcome different points of view. We are happy to discuss the relative merits of different solutions off line, as we realize that this is a complex topic. It is however interesting that we have been approached by a few FPGA companies interested in this solution, and they have not expressed prior knowledge of an alternative solution. Please feel free to contact us at any time, we are happy to discuss.- Stellamar

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