Breaking News
Design How-To

How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs

NO RATINGS
More Related Links
View Comments: Threaded | Newest First | Oldest First
Max The Magnificent
User Rank
Blogger
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Max The Magnificent   1/18/2011 8:25:43 PM
NO RATINGS
I don't know about you, but I think this is very, VERY interesting. I can think of all sorts of applications where the ability to implement one or more All-Digital ADCs in a purely digital FPGA would offer all sorts of advantages...

xjordanx_#1
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
xjordanx_#1   1/20/2011 11:39:57 AM
NO RATINGS
Hmmm... reminds me of the 12-bit ADCs that Boss (Roland) used to implement in their audio effects units of the 1980's. Though they did not have an LVDS input (wasn't invented yet!) they used a 311 comparator instead, with an R-2R ladder. If you have enough pins and you are using a low-cost FPGA you could take the same approach, albeit with successive approximation, and not have to pay a royalty... :-)

mngardon
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   1/20/2011 4:51:24 PM
NO RATINGS
Thanks for the comment! Stellamar IP does not require any external precision components. In other words we do not need an external DAC, R-2R ladder or comparator.

martinm_de
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
martinm_de   1/20/2011 12:43:12 PM
NO RATINGS
This is nothing new http://www.colognechip.com/asic/ip-cores/c3-codec-presentation_socip.pdf

mngardon
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   1/20/2011 4:54:11 PM
NO RATINGS
Thanks for the comment! Our All Digital ADC is very different than previous paper and claims, such as the one mentioned. We have better performance using a 10MHZ clock on several different FPGA families within Xilinx, Altera and Actel. We'd be happy to talk about it some more with you at any time.

WSFPGA
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
WSFPGA   1/20/2011 2:30:02 PM
NO RATINGS
Many times the "new" techniques are the most old techniques, sorry Max but nothing new here, this solution coming being used with microcontrollers since many years; the most old App Note that I know was written by Motorola. ( Try Google,is very very old I don't remember the name ) I'm using this solution - implemented with FPGA - into several customers projects since several years. Walter

Max The Magnificent
User Rank
Blogger
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Max The Magnificent   1/20/2011 2:37:03 PM
NO RATINGS
Bummer -- I was really excited -- but maybe they have a new twist -- I will ask them to comment -- Max

mngardon
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   1/20/2011 4:56:20 PM
NO RATINGS
We are unaware of this ADC technique and could not find the referenced paper in any of our research conducted over the last 2 years. Could you please provide additional information on this ADC implementation, such resolution, bandwidth and master clock.

WSFPGA
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
WSFPGA   1/20/2011 8:25:33 PM
NO RATINGS
I could be wrong, the blocks diagrams showed by Stellamar are so generic but the technique appears to be the same used in Xilinx "XPS Delta-Sigma Analog to Digital Converter (ADC)". Our solution use a different approach. Walter

mngardon
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   1/21/2011 9:34:06 PM
NO RATINGS
WSFPGA- Stellamar achieves better performance at a much slower clock. The Stellamar approach is not at all like the Xilinx approach. Stellamar

James.Ma
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
James.Ma   1/20/2011 3:50:24 PM
NO RATINGS
The input voltage & current range is limited to what the LVDS buffer can handle. Not bad but it's not going to put ADI out of business.

mngardon
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   1/20/2011 5:04:42 PM
NO RATINGS
Thanks for the comments everyone! We welcome different points of view. We are happy to discuss the relative merits of different solutions off line, as we realize that this is a complex topic. It is however interesting that we have been approached by a few FPGA companies interested in this solution, and they have not expressed prior knowledge of an alternative solution. Please feel free to contact us at any time, we are happy to discuss.- Stellamar

studleylee
User Rank
Manager
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
studleylee   1/20/2011 6:35:36 PM
NO RATINGS
Brilliant application!

old account Frank Eory
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
old account Frank Eory   1/20/2011 8:26:34 PM
NO RATINGS
Best of luck guys!

dougwithau
User Rank
Manager
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
dougwithau   1/20/2011 11:07:44 PM
NO RATINGS
I have lived with a similar design. The bug ugly thing that was not mentioned is settling time. This looks like the ADC with a PWM driving one side of a comparator and the analog input on the other pin. The settling time of the RC network that filters the PWM limits what you can measure. If the input can have step changes, then the PWM has to change, wait for the RC to settle and then see if the comparator flipped. Repeat. If the RC settling time is slow, this takes seconds to get any real accuracy. One thing that helps, and I think Max suggested this in his book, swap the bits from the counter into the digital comparator for the PWM. The PWM output through the RC network is still 50% at 50% duty cycle, but it changes at the count frequency, not 1/2 the total PWM frequency. I hope that makes sense to someone else.

mngardon
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   1/21/2011 12:25:33 AM
NO RATINGS
dougwithau- Based on your example, the settling time will in fact affect the resolution and bandwidth. With the Stellamar IP settling time of the filter is not an issue due to proprietary signal processing.

jose.quero
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
jose.quero   1/21/2011 6:58:59 PM
NO RATINGS
You can read a similar work in EDN: D/A converter ASIC uses stochastic logic EDN October,1996. pp 86-90. J. M. Quero, C. Janer, J. G. Ortega y L. G. Franquelo If you are interested in analog processing of digital signal, I also recommend: Fully Parallel Stochastic Computation Architecture IEEE Trans. on Signal Processing. August, 1996. pp 2110-2117. C.L.Janer, J.M. Quero, J. G. Ortega y L.G. Franquelo If you are interested in this topic, you may send an email to quero@us.es

mngardon
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   1/21/2011 9:40:14 PM
NO RATINGS
Jose, Thanks for the comment. Yes DACs have been mostly digital for a long time and digital DACs are widely used, as opposed to partially digital ADCs, which are not widely adopted since very few exist with usable performance. Great papers! Stellamar

acollins
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
acollins   1/24/2011 11:32:59 AM
NO RATINGS
AC performance looks good but can you tell us a little more about DC accuracy performance? (Achieving low gain error / TUE for example). This is where I've seen issues with techniques like this in the past. Many of the applicatons listed above required good DC accuracy. The DAC output (FPGA IO supply voltage) defines the ADC input range (reference) but this can vary significantly due to many factors. Also noise from other switching IOs in the same bank can be an issue.

mngardon
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   1/24/2011 8:30:56 PM
NO RATINGS
acollins, Thank you for the insightful comment. Your analysis is correct. Even though Stellamarís ADC is digital, like in any design requiring the use of traditional ADCs with the same resolution, special attention must be paid to the board layout to minimize noise and to the power supply accuracy and stability. In particular, the ADC I/O cells need to have a separate power supply. Also, they need to be placed in different banks or, if in the same bank, far away with respect to those used for other purposes to minimize interference. With a careful board design, Stellamarís ADCs have very good DC performance. Also, compared to other traditional ADCs, Stellamarís Digital ADCs have the further advantage of offering extremely low offset drifts. If you have further questions, we'd love to hear them. Please feel free to contact us at any time.

acollins
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
acollins   1/24/2011 10:02:20 PM
NO RATINGS
thanks, What are the logic resource requirements (digital core)for the example shown above?

mngardon
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   1/25/2011 12:35:43 AM
NO RATINGS
These number are from summary reports and are dependent on resolution. For an 11 bit 5kHz Digital ADC: approximately 3-4% of Altera, Cyclone III EP3C25F324C6 or 13%-16% of a Actel, ProAsic3 A3PE1500 208PQFP, or 18%-22% of a Xilinx, Spartan 3AN XC3S400AN-5FGG400. -Stellamar

sharps_eng
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
sharps_eng   1/24/2011 8:56:46 PM
NO RATINGS
I often find myself mentioning Greenarrays in these posts, but maybe that's because they are so innovative. Their ADC is ridiculously fast, but uses an on-schip VCO as the analog-to-digital element, so more suited to ASIC than FPGA. Anyone remember the old joystick interfaces? Flip a port pin and wait until an external RC discharged to give you a logic low. The C is optional if you're fast enoughj to use stray capacitance - needs calibration, though. External signal conditioning is almost always needed so adding a comparator to that is no big deal, and then you don't need an LVDS port and your FPGA gets cheaper. So where are Stellamar innovating? The first clue is in saying the settling time of the RC network is not a factor because of clever DSP... hmmm, that is so counter-intuitive I would appreciate a bit more explanation.

mngardon
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   1/25/2011 12:32:39 AM
NO RATINGS
We appreciate your comment. Most of the FPGAs offer LVDS ports with negligible cost increase. External comparators with enough performance to achieve resolutions of 12-14 bits are not cheap and furthermore they use precious board space. It is important to remember that the innovation is in the performance characteristics that we are getting when compared to other published techniques. If someone argues that this is just like the Xilinx technique, and then you compare performance and see Stellamar's performance is better, it is by definition innovative. At present Stellamarís ADCs reach up to 14 bits of resolution at 500 Hz bandwidth, 12 bits up to 15 kHz bandwidth, and 11 bits up to 20 kHz bandwidth with clocks of about 10 MHz. Development is continuing to support higher bandwidths and resolutions. Techniques proposed by Xilinx, Altera and Lattice, besides not achieving this performance, require much higher clocks. This is what Stellamar is innovating. The DSP may seem counter-intuitive, but the performance characteristics should be all you need to make up your mind. -Stellamar

Subhash.Dubey
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Subhash.Dubey   1/26/2011 11:01:23 AM
NO RATINGS
Please can I have the IP cores for ADC for digital design that can be used in FPGA kit

Max The Magnificent
User Rank
Blogger
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Max The Magnificent   1/26/2011 3:18:19 PM
NO RATINGS
Hi there -- I think the idea is that you have to license these cores -- Max

Subhash.Dubey
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Subhash.Dubey   1/26/2011 11:02:31 AM
NO RATINGS
Please suggest the IP cores of ADC if any ,for FPGA based design

Max The Magnificent
User Rank
Blogger
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Max The Magnificent   1/26/2011 3:19:03 PM
NO RATINGS
This article was written by the guys at Stellamar -- they have created these cores and they license them for use...

BurtB
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
BurtB   1/26/2011 11:27:17 PM
NO RATINGS
I feel bad that Max had to explain that Stellamar is licensing the IP Core of this ADC. Good luck Dubey, and read a bit more carefully next time.

Max The Magnificent
User Rank
Blogger
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Max The Magnificent   1/27/2011 3:06:23 PM
NO RATINGS
To be fair, I don;t think the article explicitly mentions licensing the IP... that's more something we all understand... at least we all do now :-)

harryadi
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
harryadi   1/27/2011 4:42:35 AM
NO RATINGS
This is an old technique from at least 1980. I saw this on a four bit COPS microcontroller. The app note is still on the National web site. http://www.national.com/ms/CN/CN-1.pdf The only modernization is using the LVDS rx instead of a junk comparator.

mngardon
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   1/27/2011 5:06:45 PM
NO RATINGS
It is true that we are using an LVDS IO instead of a comparator and that is where the similarity ends. The national implementation is a digital solution, however the maximum resolution they could achieve was 7-8 bits with an error of typically 15%. Stellamarís solution is novel and we have achieved resolutions up to 14 bits with an error of less than a percent. We continue to improve our technology and have the capability to achieve even higher resolutions.

Etmax
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Etmax   1/27/2011 7:22:06 AM
NO RATINGS
Excuse me, but that's effectively an SAR ADC with a PWM DAC as the DAC portion, and bleedingly obvious. As mentioned by others here it's been done with a comparator externally before. I don't know what your IP position is, but patents do not apply as there is too much prior art and the solution is immediately obvious to any one trained in the craft, only copyrights for your RTL apply. If anyone else twiddles a bit of VHDL etc. to achieve this they can implement it without royalties.

jdone
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
jdone   1/27/2011 7:01:51 PM
NO RATINGS
Etmax, There are some standard performance differences between the two approaches. SAR ADCs with PWM DACs require extremely high clocks to achieve very small bandwidths. For instance Xilinx XPS ADC requires a clock of 40 MHz to achieve a bandwidth of only 868 Hz with 9-bit resolution. A bandwidth of 2170 Hz with the same resolution requires a clock of 100 MHz. A bandwidth of 20 kHz would require an impractically high clock. http://www.xilinx.com/support/documentation/ip_documentation/xps_deltasigma_adc.pdf Stellamarís ADCs are based on a novel IP which allows to achieve much higher bandwidths and resolutions at much slower clocks. 14 bits at 500Hz bandwidth for instance, or 12 bits at 15kHz. This solution is not immediately obvious. -Stellamar

mngardon
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   1/27/2011 7:20:32 PM
NO RATINGS
also to add, the clock rates are 10-20mHz for the Stellamar implementations.

Etmax
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Etmax   1/28/2011 12:04:26 AM
NO RATINGS
Ok, I see your point. Thanks. Now I am intrigued :-)

jpontes
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
jpontes   1/27/2011 11:59:30 AM
NO RATINGS
Hi, I guess you are 7 years late. A paper about this was already published at ISCAS 2004. Taking advantage of LVDS input buffers to implement sigma-delta A/D converters in fpgas.

mngardon
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   1/27/2011 7:25:23 PM
NO RATINGS
Thanks for pointing out the paper. We are not trying to say that using an LVDS is what's novel here, rather it is the performance attained. The paper deals with an ADC implemented with an Altera FPGA. The only things in common with Stellamarís solution are the use of an LVDS input and an external filter. The ADC described in the paper offers only a maximum resolution of 9 bits with a 20 kHz bandwidth, but it requires a 50 MHz clock. Also, the paper mentions that the ADC has been characterized with input signals from 100 Hz to 20 kHz. This suggests that the ADC might not work properly at frequencies below 100 Hz. Stellamar uses a novel IP which allows to dramatically improve the performance. Stellamarís digital ADC can achieve the same bandwidth of the ADC described in the paper with a higher resolution and a much lower clock. Furthermore Stellamarís ADCs have good DC performance as well.

DanBurton
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
DanBurton   1/27/2011 11:07:21 PM
NO RATINGS
Let's see two histograms of a 20kHz input sine wave: one for your system and one for a commonly available delta-sigma ADC or even a SAR ADC. We need to see the SNR and Noise (SINAD) of your solution. Otherwise it's just not a fair comparision.

DanBurton
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
DanBurton   1/27/2011 11:16:46 PM
NO RATINGS
I mean SNR and Distortion (SINAD)

zeeglen
User Rank
Blogger
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
zeeglen   1/27/2011 11:54:16 PM
NO RATINGS
Also would be nice to see lower frequencies such as 100 Hz, 1 KHz with harmonics comparison. Non-averaged.

mngardon
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   1/28/2011 12:15:36 PM
NO RATINGS
Dan, Thanks for the interest in our technology. At the parity of resolution and bandwidth Stellamarís ADCs produce FFTs similar to traditional ADCs. In other words, for instance, a 14-bit digital ADC with a 500 Hz bandwidth has the same performance as a 14-bit Sigma-Delta ADC with the same bandwidth. The key difference is in the implementation: Stellamarís ADCs do not require analog blocks. In our article we show two FFTs of a 10-bit digital ADC implemented with a Xilinx FPGA for a 15 kHz signal input at maximum input level and at -60 dB. The S/(N+THD) measurements are respectively 60 dB and 2 dB computed over a bandwidth of 20 kHz. For more plots and measurements you can download the user guide of our evaluation board.

bcarso
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
bcarso   2/2/2011 5:04:57 PM
NO RATINGS
Independent of the merits of this approach is the fundamental misnomer "All-digital"! As Bruno Putzeys has cogently expressed, the digital domain is the symbol domain. Does the performance of this or any similar approaches depend on specifics of voltages and timings? You bet it does!---therefore it is prima facie NOT digital. The prevalent conflation of "digital" with "switching" is responsible, among other things, for the notion that power amplifiers with switching output stages (preceded by digital-domain modulators) are somehow "digital". They are not---the precise details of the switching and the power supply fluctuations are critical to the accuracy! Perhaps Stellamar has done wonderful things in the truly digital core of these things, but it is wrong to call the approach "all-digital". What for example are the characteristics of the output that drives the R-C network? Does it matter what the voltage swings and rise-fall time details are? You betcha! At that point you are in the analog domain folks, as much as you are at the LVDS front end.

Max The Magnificent
User Rank
Blogger
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Max The Magnificent   2/2/2011 5:30:49 PM
NO RATINGS
Picky, picky, picky... :-)

bcarso
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
bcarso   2/2/2011 6:29:12 PM
NO RATINGS
Someone has to be Max. I have been listening to marketing types spouting nonsense for all too many years now, and in particular in audio engineering. It has set us back for the most part. You know why "digital" power amps are getting better now? It's because they have added analog-domain correction techniques (including ADCs) to straighten out their otherwise hideous power supply sensitivities.

Max The Magnificent
User Rank
Blogger
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Max The Magnificent   2/2/2011 6:37:04 PM
NO RATINGS
I hate the marketing bull as much as the next guy -- and I agree that there are analog characteristics associated with the couple of external discrete components they use, but... If I were working at Stellamar and I was trying to describe this technology, I think I would prefer to say "All-Digital ADC" on the basis that this grabs your attention and better-conveys what you are trying to say than "Almost All-Digital ADC" or "Mostly Digital ADC". Come on ... be fair ... if this was your baby, what would you call it? :-)

Etmax
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Etmax   2/2/2011 11:31:38 PM
NO RATINGS
On "digital" audio amps, they are only suited for PA and TV applications, not HiFi even though some would have us believe that. They sound like grated cheese compared to smooth silk. I'm not sure it's all down to power supply sensitivity.

Amcfarl
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Amcfarl   2/3/2011 11:31:38 AM
NO RATINGS
First, It's not 'all digital', a comparator is an analogue part! Second, the feedback which is integrated by two analogue filter poles, is a digital signal with an analogue level of the supply voltage. Unless that's extremely well regulated DC and filtered from noise spikes (analogue again) or replaced by a switched analogue reference it'll vary all over the place. It's really a delta-sigma design where the integrator is replaced by the two pole filter and then (presumably) the data is decimated by the core DSP to reduce noise.

mngardon
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   2/3/2011 9:15:49 PM
NO RATINGS
Thanks for your comment. From the view point of engineers using Stellamar IP, the ADC is digital, because, except for a few external resistors and capacitors with non-critical values, it requires only cells available in digital libraries. For instance, the LVDS receiver we are using as a comparator is available in ASIC digital libraries and it is also available in most of the FPGAs. Even though the ADC is implemented with digital components, special attention must still be paid to the board layout to minimize noise and to the power supply stability and accuracy. As regards the technique you described (delta-sigma design where the integrator is replaced by the two pole filter), a similar technique is used by Altera and Lattice. However Stellamar IP is based on a different approach which allows to increase the ADC performance using at the same time a much slower clock.

Etmax
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Etmax   2/3/2011 11:49:02 PM
NO RATINGS
Dear mngardon, I think you are missing the point some are making. Your design is not all digital, it is maybe 99% compared to 98 or 97% (figures just for purposes of explanation) on another design. 100% would be the signal goes onto a standard digital input buffer and comes out as a data word somewhere. ANY R's and C's anywhere (apart from supply line decoupling) and any controllable thresholds and you've just left the digital domain. I'm not trying to detract from your actual achievement, just clarifying a point.

mngardon
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   2/4/2011 3:20:25 PM
NO RATINGS
The key feature of Stellamarís ADC is that it can be embedded in totally digital chips such as FPGAs. This is what we tried to capture with the name ďall digital.Ē †We could have called it "Almost All-Digital ADC" or "Mostly Digital ADC" as Max suggested or maybe, following your examples, ď99% Digital ADC.Ē However people would have asked us immediately : ďWhat does Almost All Digital †or Mostly Digital mean? Is it equivalent to Fully Digital? How did you come up with 99% Digital? After all †as Shakespeare said "What's in a name? That which we call a rose by any other name would smell as sweet."

bcarso
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
bcarso   2/3/2011 4:02:54 PM
NO RATINGS
I agree with Etmax that there is more wrong with "digital" audio amps than just PS sensitivity---as much as I could go on about them, it's not germane to the article at hand. But one aspect (absent the use of analog feedback) is that the finite switching stage Z and the output reconstruction filter interact with the loudspeaker load and introduce anomalies in the frequency response. Max, I don't know what I would call it if it were "my baby". I agree that the "all-digital" gets more attention, and that's mostly because of ignorance of what the digital domain really consists, and the unremitting hype that's been brainwashing people for many years, and driving students away from really understanding the subtle details of electronics. The authors even start their article talking about how bothersome analog design is, so to speak. I continue to hear people expressing the notion that analog design is unnecessary and obsolete. I've heard that going on for twenty-five years now. There are many wonderful things about the symbol domain, and I embrace it happily where it is appropriate. And there may be many fine attributes about this particular IP. But let's keep terminology precise and accurate.

bcarso
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
bcarso   2/4/2011 12:55:35 AM
NO RATINGS
And another thing: it is implied that using parts nominally associated with the symbol domain means the design is thus digital. But that's silly. I can use any number of gates, flip flops, etc. in a design, whether part of an FPGA or in individual packages, and the determination of what is digital is determined by HOW the parts are used. If at some point in such a circuit, the precise voltage levels and other parameters are important to the function, then there I am using that part in the analog domain! If the system shrugs off parameter variations as long as the 1's and 0's are correctly recognized, then the part is being used in the digital domain. The final output from the FPGA driving the filter network is, functionally, an analog output. Levels, timing, rise/fall times matter.

mngardon
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   2/4/2011 3:21:24 PM
NO RATINGS
All the digital components of Stellamarís ADCs implemented in FPGAs or ASICs are used in compliance with the digital specs and therefore in the digital domain. The power supply for the ADC I/Os needs to have the accuracy and stability †for the required resolution. Also, the ADC I/O cells need to have a separate power supply. The output cells are selected to drive the filter load properly, thus allowing to achieve the required performance.

RaulHuertas
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
RaulHuertas   3/10/2011 3:16:57 PM
NO RATINGS
I'm trying to descipher how it works. The no LVDS output must be a PWM output, and the R-C ladder must be a low-pass filter. LVDS must be used as a comparator right? and the processing is successive aproximations... ingenious!. PWM resolution limits ADC resolution, and the band pass filter must limit sample rate. Now I gonna read all your posted references my friends. bye! thank you!

mngardon
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   3/14/2011 5:02:33 PM
NO RATINGS
RaulHuertas:Thank you for reading all of the other comments and thank you for your support. Your assumptions of how we arrive at our solution are in the ballpark. However, we do lot more in our implementation which results in higher performance, such as improved resolution and bandwidth with a significantly slower clock. I think some of the confusion in the comments comes from us doing a poor job of explaining where we are innovating. We thought that providing performance results would be enough, and that readers could check the numbers against the published papers (many of which were cited by commentors). We could have probably called that out better, but we didn't want to seem like we were putting down anyone else's innovations. When you look at the performance numbers it becomes quite obvious that something unique is happening there. We are in talks with several of the FPGA companies and we can not comment further about how it works. Thanks again for your support, and please contact us if we can assist you or a customer in any way.

RaulHuertas
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
RaulHuertas   3/10/2011 3:38:53 PM
NO RATINGS
OMG, jsut read your coments: How bitter!

Max The Magnificent
User Rank
Blogger
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Max The Magnificent   3/10/2011 3:43:07 PM
NO RATINGS
I agree -- some folks seem really unhappy for some reason that I don't fully understand...

jackytr
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
jackytr   3/13/2011 4:17:40 PM
NO RATINGS
Xilinx has a 12-bit 1Msps ADC integrated in its 28nm FPGAs. Why not just use that hard block?

mngardon
User Rank
Rookie
re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   3/14/2011 5:04:08 PM
NO RATINGS
Jackytr: Xilinx,and others, have mixed signal FPGAs with analog ADCs, which are pricey. We are simply providing an alternative. For example, what if you are higher volume, are always cost cutting, and really only need a 10 bit ADC? You could use a lower cost part, our IP and save a bunch of money. What if you have a space application? The part you referred to is not rad hard or rad tolerant. With our IP you could essentially get a rad hard ADC on a rad hard FPGA very easily. Similar alternative exist now if you are looking to lower power and board space. Please let us know if you need more clarification.

Radio
NEXT UPCOMING BROADCAST
EE Times Senior Technical Editor Martin Rowe will interview EMC engineer Kenneth Wyatt.
Top Comments of the Week
Like Us on Facebook

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Times on Twitter
EE Times Twitter Feed
Flash Poll