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How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs

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mngardon
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re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   2/3/2011 9:15:49 PM
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Thanks for your comment. From the view point of engineers using Stellamar IP, the ADC is digital, because, except for a few external resistors and capacitors with non-critical values, it requires only cells available in digital libraries. For instance, the LVDS receiver we are using as a comparator is available in ASIC digital libraries and it is also available in most of the FPGAs. Even though the ADC is implemented with digital components, special attention must still be paid to the board layout to minimize noise and to the power supply stability and accuracy. As regards the technique you described (delta-sigma design where the integrator is replaced by the two pole filter), a similar technique is used by Altera and Lattice. However Stellamar IP is based on a different approach which allows to increase the ADC performance using at the same time a much slower clock.

bcarso
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re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
bcarso   2/3/2011 4:02:54 PM
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I agree with Etmax that there is more wrong with "digital" audio amps than just PS sensitivity---as much as I could go on about them, it's not germane to the article at hand. But one aspect (absent the use of analog feedback) is that the finite switching stage Z and the output reconstruction filter interact with the loudspeaker load and introduce anomalies in the frequency response. Max, I don't know what I would call it if it were "my baby". I agree that the "all-digital" gets more attention, and that's mostly because of ignorance of what the digital domain really consists, and the unremitting hype that's been brainwashing people for many years, and driving students away from really understanding the subtle details of electronics. The authors even start their article talking about how bothersome analog design is, so to speak. I continue to hear people expressing the notion that analog design is unnecessary and obsolete. I've heard that going on for twenty-five years now. There are many wonderful things about the symbol domain, and I embrace it happily where it is appropriate. And there may be many fine attributes about this particular IP. But let's keep terminology precise and accurate.

Amcfarl
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re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Amcfarl   2/3/2011 11:31:38 AM
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First, It's not 'all digital', a comparator is an analogue part! Second, the feedback which is integrated by two analogue filter poles, is a digital signal with an analogue level of the supply voltage. Unless that's extremely well regulated DC and filtered from noise spikes (analogue again) or replaced by a switched analogue reference it'll vary all over the place. It's really a delta-sigma design where the integrator is replaced by the two pole filter and then (presumably) the data is decimated by the core DSP to reduce noise.

Etmax
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re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Etmax   2/2/2011 11:31:38 PM
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On "digital" audio amps, they are only suited for PA and TV applications, not HiFi even though some would have us believe that. They sound like grated cheese compared to smooth silk. I'm not sure it's all down to power supply sensitivity.

Max The Magnificent
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re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Max The Magnificent   2/2/2011 6:37:04 PM
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I hate the marketing bull as much as the next guy -- and I agree that there are analog characteristics associated with the couple of external discrete components they use, but... If I were working at Stellamar and I was trying to describe this technology, I think I would prefer to say "All-Digital ADC" on the basis that this grabs your attention and better-conveys what you are trying to say than "Almost All-Digital ADC" or "Mostly Digital ADC". Come on ... be fair ... if this was your baby, what would you call it? :-)

bcarso
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re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
bcarso   2/2/2011 6:29:12 PM
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Someone has to be Max. I have been listening to marketing types spouting nonsense for all too many years now, and in particular in audio engineering. It has set us back for the most part. You know why "digital" power amps are getting better now? It's because they have added analog-domain correction techniques (including ADCs) to straighten out their otherwise hideous power supply sensitivities.

Max The Magnificent
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re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Max The Magnificent   2/2/2011 5:30:49 PM
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Picky, picky, picky... :-)

bcarso
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re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
bcarso   2/2/2011 5:04:57 PM
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Independent of the merits of this approach is the fundamental misnomer "All-digital"! As Bruno Putzeys has cogently expressed, the digital domain is the symbol domain. Does the performance of this or any similar approaches depend on specifics of voltages and timings? You bet it does!---therefore it is prima facie NOT digital. The prevalent conflation of "digital" with "switching" is responsible, among other things, for the notion that power amplifiers with switching output stages (preceded by digital-domain modulators) are somehow "digital". They are not---the precise details of the switching and the power supply fluctuations are critical to the accuracy! Perhaps Stellamar has done wonderful things in the truly digital core of these things, but it is wrong to call the approach "all-digital". What for example are the characteristics of the output that drives the R-C network? Does it matter what the voltage swings and rise-fall time details are? You betcha! At that point you are in the analog domain folks, as much as you are at the LVDS front end.

mngardon
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re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
mngardon   1/28/2011 12:15:36 PM
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Dan, Thanks for the interest in our technology. At the parity of resolution and bandwidth Stellamarís ADCs produce FFTs similar to traditional ADCs. In other words, for instance, a 14-bit digital ADC with a 500 Hz bandwidth has the same performance as a 14-bit Sigma-Delta ADC with the same bandwidth. The key difference is in the implementation: Stellamarís ADCs do not require analog blocks. In our article we show two FFTs of a 10-bit digital ADC implemented with a Xilinx FPGA for a 15 kHz signal input at maximum input level and at -60 dB. The S/(N+THD) measurements are respectively 60 dB and 2 dB computed over a bandwidth of 20 kHz. For more plots and measurements you can download the user guide of our evaluation board.

Etmax
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re: How to implement *All-Digital* analog-to-digital converters in FPGAs and ASICs
Etmax   1/28/2011 12:04:26 AM
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Ok, I see your point. Thanks. Now I am intrigued :-)

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