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How to instrument your design with simple SystemVerilog assertions

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DrFPGA
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re: How to instrument your design with simple SystemVerilog assertions
DrFPGA   3/12/2011 2:09:50 AM
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This seems like alot of work to me. Are there any rules of thumb covering what % of design time is required to implement this?

ping_yeung
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re: How to instrument your design with simple SystemVerilog assertions
ping_yeung   2/8/2011 5:52:57 AM
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Some readers would like to learn more about Assertion Based Verification. I would recommend the free Verification Academy (verification-academy.com) organized by Harry Foster. There is a module focusing on Assertion Based Verification.

jnhong
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re: How to instrument your design with simple SystemVerilog assertions
jnhong   2/3/2011 3:34:31 PM
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Excellent article, Dr. Yeung. The examples you show are very practical and commonly encountered (and even more commonly overlooked, but that's another story). This is a very good foundation to start with in planning verification. In addition, I find your writing to be wonderfully clear and concise. No fluff, very precise, and no ambiguity in message and intent. Great work!

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