Several automotive systems will require the performance improvements without the associated power problems that can be realized with multicore microcontrollers. The figure below shows how future processors with multiple cores will interact with an AUTOSAR (AUTomotive Open System ARchitecture) runtime environment (RTE). The block diagram can be viewed from two different perspectives. First, there is a vertical split that is centered around the software application. This partition has a computational shell for application management of the OEM’s software and a peripheral shell for I/O management and sensor and actuation control for TIER1 software. Second, there is a horizontal split that is centered around AUTOSAR. In this portion, one core implements the full OS and the other provides interprocessor communication via the AUTOSAR RTE. However, each OS Application may run equally on each core.
Future automotive architectures will enable software partitioning in multiple cores through AUTOSAR-compatible software.
Safety applications, such as electric power steering, can benefit from dual-core MCUs. Fabricated in a 90-nm, low-power process, the MPC5643L dual-core processor
has a frequency operating range up to 120 MHz. In safety applications, its two cores are utilized to build a redundant system, executing identical code to avoid the use of a second, redundant MCU. The results are compared on-chip and as long as they match, it is assumed the result is correct. If not, an error is flagged for further handling within the system. In addition to this lock step mode (LSM), the MPC5643 also has a decoupled parallel mode where each CPU and its subsystems run independently.
For body applications, the MPC5668G
is a recent dual-core approach with the capability to operate at frequencies up to 116 MHz. This is not like previous I/O processor, communications processor module (CPM), or XGATE approaches (See sidebar, next page: Multiple Core Déjà vu?). The MPC5668G has a true secondary microcontroller core that runs from the same instruction set as the primary core. If an application has parallel tasks, the system designer can assign one task to run on one processor kernel and the other task on the other. The process is similar to the way multiple tasks are handled by a PC. With the dual core approach, power requirements still increases but not in a linear way.
The figure below shows the block diagram of the MPC5668G, a single-chip automotive gateway MCU. Unlike the MPC5643L that uses two identical cores for redundancy in safety applications, the MPC5668G uses asymmetric, code-compliant Power architectures cores. The cores run in a different performance class. The main processor is a Power Architecture e200z6 core and the secondary is an e200z0. This configuration demonstrates the flexibility that can be used in the design of dual-core processors.
The MPC5668G block diagram shows the two Power Architecture cores, the FlexRay and Fast Ethernet controller (FEC), and other key peripherals. The MPC5668G package is a 17 x 17 mm 208 pin MAPBGA, an approach already used in high-performance automotive MCUs.