Each smaller sub-micron process technology brings a new set of physical problems for IC designers. Among the toughest of these problems are meeting electrical parasitic constraints and minimizing signal integrity issues in the interconnect routing while still reaching routing completion, controlling power consumption, staying within the specified die-size and speeding time to market. For digital designs, some of these concerns are addressed by automatic place and route tools. However, for custom IC designs, these issues remain largely unaddressed due to the inadequacy of the automation tools. In addition to custom design tools and flows, there is a need for standardization of data, including design constraints, an effort which is starting to gain momentum at the industry level.
This paper details the increasing problem of achieving parasitic-constraint closure during interconnect routing and how a shape-based routing methodology can help to solve these problems automatically while completing the routing of the design.
In electronic circuit design, parasitics are unintended electrical effects, including resistance (R), capacitance (C) and inductance (L), caused by the electrical interaction of the various components and wiring structures of the circuit. Using older process technologies, the parasitic effects of the transistors themselves had the greatest impact on circuit performance. Basically, if a silicon designer did a reasonable job of placement, the vast majority of parasitic and signal-integrity issues were solved already prior to detailed routing. Routing tools could simply concentrate on connecting the circuit according to the design rule checker (DRC) rules while minimizing wire length. However, this approach no longer works today. The widespread adoption of sub-micron technologies has brought about a new set of issues that the designer has to consider, and a new set of challenges for the electronic design automation (EDA) software used in the design process.
Prior to sub-micron design, parasitic constraints (including timing) and signal integrity issues were considered to be second-order effects, but with today’s advanced process geometries, these are now first-order effects. Interconnect delay is the major contributory factor to these issues. The problem is that the increasing number of ever-thinner – and therefore relatively “taller” – wires of sub-micron process technologies has less space between each wire, which causes cross-capacitive coupling among other parasitic effects. Therefore, routing technologies need to consider parasitic constraints and effects of the interconnect continuously during the routing process in order to achieve both routing completion and constraint closure efficiently.
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