Electrocardiography (ECG) is the acquisition of electrical activity of the heart captured over time by an external electrode attached to the skin. Each of the cell membranes that form the outer covering of the heart cell have an associated charge which is depolarized during every heart beat. These appear as tiny electrical signals on the skin which can be detected and amplified by the ECG.
The first practical ECG was invented by Willem Einthoven in the early 1900’s. The system was bulky and required many people to operate it. The patient had to submerge his arms and legs into large electrode jars which contained an electrolyte solution. Present day ECG monitoring devices are compact and portable so they can be worn by a patient as he or she moves around. A 12-lead ECG for home use can be carried around in a pocket.
The term “lead” in context to an ECG refers to the voltage difference between two of the electrodes, and it is this difference which is recorded by the equipment. For example “Lead_I” is the voltage between the left arm and right arm electrodes. Lead_I and Lead_II are referred to as Limb leads. V1-V6 are referred to as chest leads. The ECG tracing V1 is the difference between the voltage at Vc1(the voltage at the electrode on the chest) and the average of Lead_I, Lead_II, and Lead_III. A standard 12-Lead ECG system consists of eight actual values and four derived values. Table 1 gives a snapshot of various lead voltages, actual and derived.
Figure 1: Typical ECG waveform.
(Click on image to enlarge)
A typical plot of an ECG is shown in Figure 1. The X-axis shows the time scale. Each box (5mm) here corresponds to 20ms. The Y-axis shows the amplitude of the signal captured. Each box on the Y-axis (5mm) corresponds to 0.5 mV. (10mm/mV and 25mm/s)
Figure 1: Typical ECG waveform.
(Click on image to enlarge)
The first step in the design of an ECG system involves understanding the nature of the signal that needs to be acquired. The ECG signal consists of low amplitude voltages in the presence of high offsets and noise. Figure 2 shows the characteristic of the ECG signal. The large offsets are present in the system due to half cell potential developed at the electrodes.
Ag/AgCl (Silver-Silver chloride) is the common electrode used in ECG systems and has a maximum offset voltage of ±300mV. The actual desired signal is ±0.5mV superimposed on the electrode offset. In addition, the system also picks up the 50/60Hz noise from the power lines which forms the common mode signal. The amplitude of the power line noise could be very high and needs to be filtered.
Figure 2: Characteristics of the ECG signal to be acquired.
Analog Front-End processing forms an important part of the ECG system since it needs to distinguish between noise and the desired signal which is of small amplitude. The front-end processing circuitry consists of an instrumentation amplifier which reduces the common mode signal. Instrumentation amplifiers that operate on ±5V are commonly used to take advantage of the large input voltage range.
The instrumentation amplifiers should have high input impedance since the skin resistance could be very large. Operational amplifiers are needed for signal conditioning for the ECG device. The signal chain for the ECG acquisition system consists of instrumentation amplifiers, filters implemented through op-amps, and ADCs.
Signal processing is a huge challenge since the actual signal value will be 0.5mV in an offset environment of 300mV. Other factors like AC power-supply interference, RF interference from surgery equipment, and implanted devices like pace makers and physiological monitoring systems can also impact accuracy. The main sources of noise in ECG are
- Baseline wander (low frequency noise)
- Power line interference ( 50Hz or 60Hz noise from power lines)
- Muscle noise (This noise is very difficult to remove as it is in the same region as the actual signal. It is usually corrected in software.)
- Other interference (i.e., radio frequency noise from other equipment)
Removal of common mode noise
Interference usually manifests as common mode noise across both terminals of the differential amplifier. This noise can be removed by the following methods:
- Isolate the front-end ground electronics from the digital system as much as possible. Effective system level design is extremely important in terms of the overall noise rejection.
- Use instrumentation amplifiers with very high common mode rejection ratios on the order of 100dB
- Drive the patient body with an inverted common mode signal. The right leg of the patient is driven with a signal which is the inverted average of Lead_I, Lead_II, and Lead_III. Scaling the suitably prevents common mode noise from being coupled into the system.
- Shield the device using metallic shields to prevent high frequency RF from being coupled into the system.
- Use shielded cables to acquire the ECG which are driven with a common voltage to reduce noise from being coupled.
- Apart from the above methods, a number of software algorithms are present for the removal of noise after the signal has been acquired.
The aim in the design of the front-end is to minimize the noise which is coupled into the system.
Removal of baseline wander
Baseline wander is a low-frequency component present in the ECG system. This is due to offset voltages in the electrodes, respiration, and body movement. This can cause problems in the analysis of the ECG waveform. The offset also limits the maximum value of gain which can be obtained from the instrumentation amplifier. At higher gains, the signal can saturate. This noise can be removed by:
- Implementing a high-pass filter using hardware. The cut-off frequency should be such that the ECG is undistorted while the baseline wander must be removed. A typical value of the cut-off frequency is 0.05Hz. Since this cut-off frequency is very low, this method requires bulky capacitors.
In this method, two stages of gain are implemented since the offset can saturate at the output of the instrumentation amplifier. The two-stage filter also makes the system more complex. This system requires a low resolution ADC, typically 8 to 16 bits of resolution. Figure 3 shows the signal chain flow for implementing the high pass filter in hardware.
Figure 3: Implementation of ECG signal chain with hardware high pass filter.
- Implementing a high-pass filter in software: One of the specifications of the ECG is the input referred noise which should be less than 30μV for the entire system at 150Hz bandwidth. For this method, we use a high resolution ADC and a single stage of gain achieved by the instrumentation amplifier. This method is more suitable since low noise amplifiers and high resolution ADCs are now available at lower prices. The hardware-based high pass filter is removed in this case, and the baseline wander is carried over into the digital domain. Filtering in the digital domain is less expensive and easy to carry out. For example, the PSoC3/5 from Cypress with its 20-bit ADC and discrete filter block enables such a topology.
When the microcontroller is also integrated into the system, the overall cost of the system is reduced. Figure 4 shows the signal-flow chain for implementing the system without the hardware high-pass filter. In this case, the digital filter block can implement effective filtering after the signal is acquired by the ADC. As can be seen from the diagram, the complexity of the front-end is reduced significantly.
Figure 4: Implementation of the ECG signal chain without a hardware high pass filter.
Removal of high-frequency noise
According to the IEC specification, the bandwidth of the ECG required is from 0.5Hz to 150Hz. However ECG machines have the means to detect pacemakers. Pacemakers can be detected either by having hardware or software dedicated to this task. If the detection has to be done in software, the sampling rate of the ADC must be of the order of 3 to 4 ksamples/sec.
The advantage of having software-based pacemakers is that changes in firmware can adapt the ECG machine to different kinds of pacemakers. Most of the high frequency noise can be filtered before it is sampled by the ADC. The device can be shielded to prevent high frequency radiated noise from being coupled. Once the data is sampled by the ADC, a digital FIR filter having the desired cut-off frequency is implemented. This removes high frequency noises in the ECG trace.
Removal of power-line noise
The amplitude of power-line noise is very large and generally gets coupled into the system, despite care to prevent common-mode noise in the digital domain. Power-line noise is removed by implementing a notch filter at 50/60Hz in the digital domain.
Firmware-based noise correction
Many software algorithms are available which help in filtering of ECG after digitization. These algorithms are often used in high-end equipment and are usually proprietary to the manufacturer. The microcontroller needs to have sufficient capacity to implement these complex algorithms.
The transfer function of the filter can be implemented in the digital domain. Care has to be taken in choosing the order of the filter. It should be high enough to enable a steep roll-off, but not so high as to prevent the effect of ringing. Used a flexible digital-filter block, the microcontroller can implement the desired frequency response needed for ECG system.
High-speed analog multiplexers allow the acquisition of various channel data, and a high input impedance instrumentation amplifier should be used external to the microcontroller to amplify the signal. The availability of a high resolution ADC on the order of 20 bits as well as integrated general-purpose op-amps enables further component reduction in the design of ECG equipment.
Figure 5: User interface to configure required filter types.
(Click on image to enlarge)
Filter design is simplified through the use of tools provided by silicon vendors such as PSoC Creator. As seen from the figure, the filter can be configured graphical using drop-down menus to specify filter parameters. Figure 5 shows a transfer function of a typical ECG system. The sampling rate is 500 samples per second. Using a two-stage filter, a notch has been implemented at 60Hz. The bandwidth of the signal is from 0.05Hz to 150Hz. The two filters have an order of 35 each. The filter block used to implement this has two channels of filters, each with a maximum of four stages.
This enables the implementation of complex filters without having to manually calculate the filter coefficients. It can also graphically display various parameters such as phase response, impulse response, step response, and so on. The use of dedicated filter blocks enables rapid development of filters tuned to a particular application.
Since the voltages at which handheld ECG equipment operate are shrinking, signal processing has become an important challenge. Being able to implementing the complete analog front-end processing in a single, mixed-signal controller, and using both integrated hardware and software, increases system accuracy and reduces overall power consumption. In this way, developers can reduce system cost tremendously by encapsulating functionality onto a single SoC platform for analog-intensive applications.
With healthcare moving towards preventive medicine, ECG equipment is becoming an important part of the diagnosis process. Technological advances in communication and low power circuit design have enabled the development of better and safer ECG devices which are portable, operate with lower power consumption, are more accurate, and have the capacity to incorporate the latest diagnostic features.
About the authors
Ajay Bharadwaj is currently working at Cypress Semiconductor Corp. as a Senior Applications Engineer. He holds a Bachelor’s degree in Electronics and Communication engineering, and was a co-founder of a medical device startup company. His interests include analog design, digital design and entrepreneurship. He can be reached at email@example.com.
Umanath Kamath works as an Applications Engineer with Cypress Semiconductor. He enjoys building analog and digital circuits and systems using different types of sensors.