Companies designing complex electronics always face numerous challenges, which keep evolving, because each problem solved enables new advances that in turn lead to new challenges. The year ahead will see increased system engineering content in chip- and board-level designs.
Problems that used to be solvable at the physical or register transfer level (RTL) are now being increasingly impacted by system architecture. Much of the challenge of low power design used to be limited to the physical implementation, but now the primary impact is at the system architecture level. As a result, system design trade-offs are becoming an increasingly important part of the job of the chip designer.
In 2011 and beyond, more and more of the design task will entail evaluating the chip architecture at the system level to optimize power and performance.
Previously, chip designers used to work independently from the embedded software developers. Now the development and verification of embedded software with hardware is the largest component of chip and system design.
Electronic design automation (EDA) companies used to ignore software and focus only on design of the chip hardware, but that has changed. For decades, integration of embedded software with hardware has been the place where the most significant problems have arisen. Although for the past 15 years EDA vendors have provided hardware/software co-verification tools, they have taken further steps recently as part of the movement towards system design. In a significant change, core development and verification of embedded software is now becoming a primary activity of EDA suppliers.
Embedded software can easily impact the power consumption of a chip design. Yet embedded software developers are usually unable to evaluate their software with quantitative measurements of expected power dissipation.
Now all this is changing, as the merger of embedded software development and verification with hardware development and verification is driving analysis tools that will provide those answers. As more of the system design becomes virtual, more of the verification for system integration will be virtual as well.
This isn't happening only with embedded software. High level electronic system-level (ESL) design tools are providing modeling capability to do power/performance trade-offs at the architectural level. Hardware /software trade-offs can provide power savings of a factor of 2. (See Fig. 1) This will be an increasing focus of EDA, and is already one of the fastest growing EDA software markets.
What specific effect are these changes likely to have on India? Whenever a new discontinuity emerges, there are lots of opportunities for new design and verification methodologies. Embedded software, coupled with hardware design and verification, is an area that has been ready for major advances for a long time. Engineers in India bring software expertise to the hardware design arena and can greatly impact the next phase of system design.
Walden C. Rhines,
Chairman and CEO
Mentor Graphics Corp.
Courtesy of EE Times India