Manufacturing closure has become a key design challenge at smaller technology nodes such as 32 and 22nm. Starting at 45/40nm, the increasing complexity of design rule checks and design-for-manufacturing rules began to stress traditional physical design flows. This trend is expected to continue and worsen at the 32/22 nm nodes, where manufacturing closure may become a serious bottleneck in design schedules.
The source of the growing manufacturing signoff challenge is the widening gap between manufacturing and design. Features get smaller, but the resolution available through lithography using 193nm light sources is reaching its limits. As we move to 32nm and beyond, the lithographic process introduces increasing variability since diffraction patterns are sensitive to specific layout shapes, and focus on the wafer becomes more sensitive to vertical topology due to depth of field effects. These factors introduce significant variations in line with width, thickness, and other physical characteristics that affect the yield and performance of ICs.
To access the full Design Article by Mentor Graphics Corp. (in PDF format), click here.
About the authors:
. Ivailo Nedelchev, principal technologist, Place and Route Division, Mentor Graphics Corp.
. Sudhakar Jilla, marketing director, Mentor Graphics Corp.
Courtesy of EE Times India